{"id":3803411,"url":"https://alion.io/job/onsemi-mixed-signal-verification-engineer","title":"Mixed Signal Verification Engineer","company":{"id":58717,"name":"onsemi","domain":"onsemi.com","url":"https://alion.io/company/onsemi","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":{"grade":"B","score":79,"open_postings":189,"ghost_share":0,"stale_share":0.857,"repost_share":0,"time_to_fill_p50_days":35,"computed_at":"2026-11-08T05:47:12Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Cork, Ireland"],"countries":["IE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"CI/CD","optional":true}],"status":"live","first_seen_at":"2026-11-05T10:38:50Z","employer_posted_date":"2026-11-05","last_verified_at":"2026-11-08T16:07:45Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"onsemi is seeking a Mixed Signal Verification Engineer to join its Core Analog IP Development Centre of Excellence in Cork, Ireland. You will verify mixed-signal IP, complex systems-on-chip (SoCs) and digital-on-top subsystems supporting the Treo platform, including power, clock, monitoring and reset functions.\nYour primary focus will be developing and executing verification plans and reusable environments that validate interactions between analog blocks and their controlling RTL/digital logic. You will combine analog/digital co-simulation with behavioural and real-number modelling to achieve appropriate accuracy, performance and coverage. Working closely with analog designers, digital designers and system architects, you will identify integration issues, debug cross-domain behaviour and provide clear evidence of verification closure. Hands-on experience using the latest mixed-signal verification tools and flows from major EDA vendors is essential.\n Mixed-Signal Verification Planning and Execution\nDevelop requirements-driven verification plans for mixed-signal IP, complex SoCs and digital-on-top subsystems, defining scenarios, checkers, coverage goals and completion criteria.\nBuild and maintain reusable SystemVerilog/UVM-based verification environments, integrating analog models and co-simulation configurations with controlling RTL/digital logic.\nVerify analog/digital interactions including register programming, handshaking, status reporting, interrupts, calibration controls and feedback between analog functions and digital control logic.\nDevelop directed and constrained-random tests for operating modes, start-up, shutdown, reset, power and clock sequencing, fault conditions and recovery behaviour.\nImplement assertions, scoreboards and functional coverage to check mixed-signal behaviour, track requirements and identify verification gaps.\nExecute regressions, analyse failures, drive coverage closure and document verification results, residual risks and readiness for design release.\nAnalog/Digital Co-Simulation, Modelling and Debug\nConfigure and run mixed-signal co-simulations combining transistor-level or behavioural analog blocks with controlling RTL/digital logic at subsystem and SoC level.\nDevelop, integrate and validate Verilog-AMS and SystemVerilog real-number models (RNM), selecting abstraction levels that balance simulation accuracy, runtime and verification objectives.\nManage analog/digital boundary behaviour, including connect modules, signal disciplines, voltage thresholds, timing, tolerances and model initialisation.\nDebug failures across analog waveforms, digital transactions and RTL control sequences; distinguish design defects from modelling, configuration and testbench issues.\nCollaborate with analog and digital design teams to correlate models with circuit behaviour and verify power, clock, monitoring and reset functions across relevant operating conditions and process, voltage and temperature corners.\nUse current-generation mixed-signal verification tools from major EDA vendors, optimise co-simulation configurations and maintain reproducible simulation and debug flows.\nCollaboration, Automation and Methodology\nWork with system architects, IP owners and integration teams to clarify requirements, identify cross-domain risks and agree verification responsibilities.\nParticipate in specification, design and verification reviews; communicate defects, coverage progress and technical trade-offs clearly.\nAutomate simulation setup, regression execution, results analysis and reporting using scripting and version-controlled workflows.\nImprove reusable verification components, modelling practices and documentation, sharing practical knowledge across analog and digital engineering teams.\n A bachelor’s or master’s degree in electrical or electronic engineering, computer engineering or a closely related discipline, with 4-8 years of relevant IC verification experience.\nDemonstrated mixed-signal verification experience on complex SoCs or digital-on-top subsystems, including co-simulation of analog blocks with their controlling RTL/digital logic.\nHands-on experience using the latest mixed-signal verification tools and current-generation simulation, modelling and debug flows from major EDA vendors such as Cadence, Synopsys or Siemens EDA, with practical proficiency in at least one major-vendor tool suite.\nStrong SystemVerilog and UVM skills, including reusable testbench development, constrained-random stimulus, assertions, scoreboards and functional coverage.\nPractical experience with analog behavioural modelling and real-number modelling using Verilog-AMS and/or SystemVerilog RNM, including model validation and integration into mixed-signal environments.\nA sound understanding of analog circuit behaviour and digital RTL, including power and clock control, reset sequencing, register interfaces and analog/digital boundary effects.\nExperience translating specifications into verification plans, debugging cross-domain failures and driving regression and coverage closure.\nProficiency with Linux-based engineering environments, version control and scripting languages such as Python, Tcl or Perl for verification automation.\nStrong analytical, communication and teamwork skills, with the ability to work independently on verification tasks and collaborate effectively across analog, digital and system teams.\nDesirable Experience\nExperience verifying automotive ICs or subsystems, with familiarity with automotive development processes, quality expectations and requirements traceability.\nFunctional safety experience, including familiarity with ISO 26262, safety requirements, fault injection, diagnostic mechanisms and verification of fault detection and safe-state behaviour.\nExperience with power-management, clocking, monitoring or reset IP, including LDOs, DC-DC regulators, bandgap references, oscillators and PLLs in BCD or other mixed-signal technologies.\nExperience with low-power verification, UPF-aware flows, firmware-driven subsystem tests, continuous integration or correlation of verification results with silicon measurements.","description_format":"text","description_chars":6128,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Analog & Power Semiconductors","Machine Vision & 3D Cameras"],"lifecycle":[{"event":"open","at":"2026-11-05T12:30:47Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely 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