{"id":1139056,"url":"https://alion.io/job/onsemi-principal-verification-engineer-3","title":"Principal Verification Engineer","company":{"id":58717,"name":"onsemi","domain":"onsemi.com","url":"https://alion.io/company/onsemi","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":{"grade":"B","score":82,"open_postings":166,"ghost_share":0,"stale_share":0.904,"repost_share":0,"time_to_fill_p50_days":3,"computed_at":"2026-09-25T05:45:01Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":41000,"max_usd":97000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":344},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-23T05:38:55Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-09-26T03:54:06Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Description - ASIC/SoC Verification Engineer\nWe are seeking an experienced Principal ASIC/SoC Verification Engineer to join our dynamic and fast-paced engineering team. In this role, you will be responsible for ensuring the functional correctness, robustness, and overall quality of our cutting-edge semiconductor and SoC designs. If you thrive in a collaborative environment and enjoy solving complex technical challenges, this opportunity is an excellent fit.\nResponsibilities\n1. Verification Planning and Execution\nDevelop and execute comprehensive SoC/IP-level verification plans aligned with design specifications and project goals.\nDrive verification closure through functional, code, and assertion coverage, ensuring high-quality deliverables.\nApply industry-standard ASIC/SoC verification techniques including test planning, testbench creation, constrained-random and directed stimulus, assertions, and coverage-driven verification.\nPerform SoC integration verification, validating interactions across subsystems, interfaces, and power/performance domains.\n2. Testbench & Environment Development\nArchitect, develop, and enhance SystemVerilog UVM/OVM-based testbenches for IP and SoC-level verification.\nBuild and integrate reusable Verification IP (VIP) and scalable verification components.\nCollaborate with internal teams and third-party VIP providers to ensure seamless integration and compliance.\nDevelop checkers, scoreboards, monitors, and coverage models to support robust verification.\n3. Methodology, Flows & Best Practices\nDemonstrate strong understanding of ASIC/SoC design and verification methodologies, including constraint-random verification and object-oriented programming principles.\nContribute to verification methodology improvements, automation, and flow optimization.\nEnsure adherence to best practices in UVM architecture, reuse, and maintainability.\n4. Advanced Verification Skills\nPerform Gate-Level Simulation (GLS) including SDF annotation, timing verification, and debug of post-synthesis/post-layout issues.\nExecute power-aware verification using UPF/CPF, validating power modes, isolation, retention, and sequencing.\nDebug complex SoC-level issues involving multiple clock domains, resets, and power states.\nApply formal verification techniques where appropriate to complement simulation-based verification.\n5. Technical Skills\nStrong proficiency in SystemVerilog (UVM/OVM) and scripting languages such as Python, Perl, Tcl, C/C++, and Verilog PLI.\nFamiliarity with standard protocols and interfaces (e.g., I2C, SPI, UART, AXI/AHB/APB).\nExperience with simulation, debug, and coverage tools from major EDA vendors (Synopsys, Cadence, Siemens).\nKnowledge of CI/regression automation, version control, and workflow tools is a plus.\n6. Collaboration & Communication\nWork effectively with design, architecture, DV, validation, and firmware teams to drive verification to completion.\nCommunicate technical concepts clearly through documentation, reviews, and cross-functional discussions.\nDemonstrate initiative, strong analytical problem-solving skills, and adaptability in a diverse team environment.\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.\n10 Years of experience in SoC/IP verification,.\nStrong expertise in SystemVerilog, UVM, and advanced verification methodologies.\nHands-on experience with ARM-based SoC architectures, AMBA protocols (AXI/AHB/APB), and system-level interactions.\nProven ability to build reusable, scalable testbench architectures.\nSolid understanding of test planning, coverage-driven verification, and verification metrics.\nExperience with GLS, timing verification, and debug.\nKnowledge of power-aware verification (UPF/CPF).\nStrong scripting and automation skills (Python, Perl, Shell, Make, etc.).\nExposure to AI/ML techniques applied to verification (e.g., intelligent stimulus generation, failure triage, coverage optimization).\nExcellent problem-solving, debugging, and communication skills.","description_format":"text","description_chars":4039,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Analog & Power Semiconductors","Machine Vision & 3D Cameras"],"lifecycle":[{"event":"open","at":"2026-09-23T09:39:25Z"}],"liveness":{"score":52,"band":"ok","label":"Likely open","p_open":1,"p_active":0.578,"p_room":0.9,"age_days":2,"expected_fill_days":3,"reasons":["conf:1","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-09-25T05:45:01Z"},"pay":null,"html_url":"https://alion.io/job/onsemi-principal-verification-engineer-3","json_url":"https://alion.io/job/onsemi-principal-verification-engineer-3.json","meta":{"generated_at":"2026-09-26T04:11:50Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4577,"day_limit":5000,"remaining_today":423,"minute_limit":60,"resets_at":"2026-09-27T00:00:00Z"}}}