{"id":196677,"url":"https://alion.io/job/onsemi-senior-design-verification-engineer-2","title":"Senior Design Verification Engineer","company":{"id":58717,"name":"onsemi","domain":"onsemi.com","url":"https://alion.io/company/onsemi","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":{"grade":"B","score":77,"open_postings":182,"ghost_share":0,"stale_share":0.901,"repost_share":0,"time_to_fill_p50_days":28,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Brno, Czech Republic"],"countries":["CZ"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":47000,"max_usd":108000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1777},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-03T00:00:00Z","employer_posted_date":"2026-09-03","last_verified_at":"2026-10-25T09:17:41Z","board_verified":true,"closed_at":null,"days_open":52,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":52},"description":"Join onsemi’s new and growing RISC-V division and help ensure the functional correctness, quality, safety, and security of configurable and customizable RISC-V CPU IP.\nYou will participate in the complete verification process, from understanding requirements and defining verification plans and strategies to implementation, debugging, metric-driven verification closure, tape-out, and delivery of reviewable evidence.\nYou will combine proven SystemVerilog/UVM simulation methodologies with innovative and advanced formal verification techniques. You will also help define practical AI-assisted verification approaches focused on measurable quality and engineering effectiveness, not simply producing unchecked AI-generated content.\nDefine and execute verification plans for RISC-V CPU features, configurations, and custom extensions.\nTranslate architecture, product, safety, and security requirements into measurable verification objectives and closure criteria.\nDevelop reusable SystemVerilog/UVM environments, assertions, checkers, reference models, coverage models, and regression infrastructure.\nVerify ISA behavior, privilege modes, exceptions, interrupts, memory interfaces, debug functionality, configurations, and custom instruction interactions.\nCombine simulation and advanced formal techniques to address complex control logic and high-risk corner cases.\nApply metric-driven verification to measure progress, identify quality gaps, and support sign-off decisions.\nDebug complex failures and collaborate with architecture, RTL design, functional safety, security, and SoC integration teams.\nExecute requirements traceability and fault-oriented verification with the rigor required to pass external safety and security assessments for multiple certification programs.\nHelp define and evaluate AI-assisted verification methods, including their benefits, limitations, quality controls, and safeguards.\nWhy join us?\nJoin a new and growing RISC-V division and help shape its verification practices, infrastructure, and engineering culture.\nWork alongside a highly skilled verification team, including principal and staff engineers with many years of CPU verification experience.\nLearn the complete CPU verification process, from planning and strategy through implementation, closure, tape-out, and assessment-ready evidence.\nJoin a team with a proven track record of delivering and taping out multiple CPUs and products with zero critical bugs.\nVerify CPU IP that will be implemented in real products and taken through silicon tape-out, not limited to research or prototypes.\nWork with proven UVM simulation methodologies and innovative formal verification techniques.\nDevelop expertise in RISC-V architecture, configurable CPU IP, custom extensions, functional safety, and security.\nHelp shape responsible AI-assisted verification practices where quality, effectiveness, and expert oversight are essential.\nContribute to CPU technologies for automotive, industrial, security, and edge-AI applications.\nStrong experience in CPU, SoC, or complex reusable digital IP verification.\nAdvanced knowledge of SystemVerilog, UVM, assertions, functional coverage, and verification debugging.\nExperience with verification planning, metric-driven execution, coverage analysis, and quality-based closure.\nUnderstanding of processor concepts such as pipelines, privilege levels, exceptions, interrupts, memory access, and debug.\nExperience with formal verification or strong motivation to develop advanced formal verification expertise.\nAbility to translate technical requirements into measurable verification objectives and reviewable evidence.\nStrong analytical, problem-solving, communication, and cross-team collaboration skills.\nA quality-oriented engineering mindset and willingness to take ownership of assigned verification areas.\nRISC-V experience is valuable. Strong verification experience with another processor architecture and motivation to develop RISC-V expertise are equally welcome.\nExperience with ISO 26262, fault-oriented verification, security verification, certification activities, or AI-assisted engineering is an advantage.","description_format":"text","description_chars":4141,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Analog & Power Semiconductors","Machine Vision & 3D Cameras"],"lifecycle":[{"event":"open","at":"2026-09-03T13:42:37Z"}],"visa":[],"liveness":{"score":21,"band":"cold","label":"Long shot","p_open":1,"p_active":0.459,"p_room":0.45,"age_days":52,"expected_fill_days":28,"reasons":["conf:9","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-10-25T05:49:26Z"},"pay":null,"html_url":"https://alion.io/job/onsemi-senior-design-verification-engineer-2","json_url":"https://alion.io/job/onsemi-senior-design-verification-engineer-2.json","meta":{"generated_at":"2026-10-25T20:25:45Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":28937,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-26T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":58717},"rest":"https://alion.io/mcp/rest/get_company?id=58717"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fonsemi-senior-design-verification-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fonsemi-senior-design-verification-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fonsemi-senior-design-verification-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/onsemi-senior-design-verification-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fonsemi-senior-design-verification-engineer-2"}]}