{"id":182221,"url":"https://alion.io/job/onsemi-sr-mts-digital-architect","title":"Digital Design Member of Technical Staff (MTS)","company":{"id":58717,"name":"onsemi","domain":"onsemi.com","url":"https://alion.io/company/onsemi","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":{"grade":"B","score":77,"open_postings":182,"ghost_share":0,"stale_share":0.901,"repost_share":0,"time_to_fill_p50_days":28,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Cork, Ireland"],"countries":["IE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":116000,"max_usd":240000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-08-31T00:00:00Z","employer_posted_date":"2026-09-21","last_verified_at":"2026-10-25T22:42:51Z","board_verified":true,"closed_at":null,"days_open":55,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":55},"description":"About onsemi\nonsemi is driving innovation in power, sensing, and automotive semiconductor solutions to enable a more sustainable future. Our Treo™ platform underpins next-generation intelligent power systems for automotive and industrial markets, emphasizing safety, reliability, and scalability.\nRole Overview\nWe are seeking a senior Digital Design Member of Technical Staff (MTS) to lead and deliver digital controller IP for power, clock, and error management subsystems within the onsemi Treo™ platform. This role is a hands-on technical leadership position, focused on architecting, designing, integrating, and evolving complex digital IP that tightly interfaces with analog and mixed-signal blocks in automotive-grade SoCs.\nThe successful candidate will bring deep experience in automotive functional safety, digital-analog co-design, and system-level integration, while also serving as a technical mentor and thought leader within the Cork design organization.\nKey Responsibilities\nArchitect, design, and implement digital system controllers for: \nPower management\nClock management\nError detection, reporting, and mitigation subsystems\nDevelop robust digital IP that controls and interacts closely with analog and mixed-signal blocks. \nOwn IP delivery from architecture through RTL, verification, integration, and silicon bring-up support. \nDrive and support digital-on-top product integration flows, including: \nIP integration into SoC environments\nClocking, reset, power domain, and safety integration\nEnsure designs meet automotive functional safety requirements (e.g., ISO 26262 concepts such as ASIL, fault coverage, diagnostic mechanisms). \nCollaborate cross-functionally with: \nAnalog design\nVerification\nPhysical design\nSystems, safety, and product engineering teams\nDefine and evolve IP roadmaps aligned with: \nPlatform strategy\nProduct requirements\nLong-term business objectives\nMentor and technically guide junior and mid-level engineers, promoting best practices in design, documentation, and review culture. \nContribute to continuous improvement of: \nDesign methodologies\nVerification strategies\nAutomation and productivity tools\nStay technically curious and engaged with emerging AI/ML applications in digital design, including their potential impact on RTL development, verification, and productivity.\n\nRequired Qualifications\n15+ years of hands-on digital design experience, primarily in ASIC or SoC development. \nProven experience delivering automotive IP with functional safety requirements. \nStrong background designing digital controllers for analog blocks (e.g., power regulators, PLLs, sensors, clocking systems). \nDeep understanding of system-level digital integration, including: \nPower and clock domain management \nReset strategies \nError handling and safety mechanisms \nSolid experience with RTL design (SystemVerilog). \nWorking knowledge of constrained-random verification methodologies, including SystemVerilog and UVM. \nDemonstrated ability to work effectively as a senior individual contributor, owning complex technical problems end to end. \nStrong communication skills and a demonstrated willingness to mentor junior engineers.\n\nPreferred / Plus Qualifications\nExperience with automotive safety standards such as ISO 26262 (concept, system, or IP-level application). \nWorking knowledge of JIRA for task tracking and JAMA for requirements management. \nExposure to safety diagnostics, fault injection, or safety verification techniques. \nExperience contributing to platform-level IP strategies or multi-generation roadmap planning. \nFamiliarity with low-power design techniques and power-aware verification. \nWhat We Offer\nOpportunity to work on industry-leading automotive and power semiconductor platforms. \nA senior, high-impact technical role with architectural ownership. \nA collaborative engineering culture with strong ties between digital, analog, and system teams. \nCompetitive compensation and benefits. \nCareer growth within a global semiconductor leader, while being based in Cork’s vibrant technology ecosystem.","description_format":"text","description_chars":4061,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Analog & Power 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