{"id":1453000,"url":"https://alion.io/job/onsemi-staff-design-verification-engineer","title":"Staff Design Verification Engineer","company":{"id":58717,"name":"onsemi","domain":"onsemi.com","url":"https://alion.io/company/onsemi","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":{"grade":"B","score":82,"open_postings":164,"ghost_share":0,"stale_share":0.902,"repost_share":0,"time_to_fill_p50_days":16,"computed_at":"2026-10-06T05:45:30Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":33000,"max_usd":68000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":459},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Formal Verification","optional":true}],"status":"live","first_seen_at":"2026-09-29T05:30:45Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-10-06T22:07:59Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"We are seeking an experienced Staff ASIC/SoC Verification Engineer to join our dynamic and fast-paced engineering team. In this role, you will be responsible for ensuring the functional correctness, robustness, and overall quality of our cutting-edge semiconductor and SoC designs. If you thrive in a collaborative environment and enjoy solving complex technical challenges, this opportunity is an excellent fit.\nResponsibilities:\nVerification Planning and Execution:Develop and execute comprehensive verification plans.\n\nClose verification with coverage closure, ensuring high-quality results.\nApply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions.\n\n Testbench Development:Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages.\nImplement reusable Verification IP (VIP) components.\nCollaborate with third-party VIP providers.\n\nMethodology and Flows:Demonstrate a solid understanding of ASIC design and verification methodologies.\nApply object-oriented programming principles effectively.\nImplement constraint random verification methodology.\n\n Technical Skills:Proficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI).\nFamiliarity with industry standards (e.g., I2C/SPI).\nExperience with low-power verification using UPF (Unified Power Format) is a plus.\nKnowledge of formal verification techniques is advantageous.\n\nCollaboration and Communication:Work effectively with internal teams and external customers.\nStrong written and verbal communication skills.\nInitiative, analytical problem-solving abilities, and adaptability within a diverse team environment.\n\n Required Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.\n10 Years of experience in SoC/IP verification,.\nStrong expertise in SystemVerilog, UVM, and advanced verification methodologies.\nHands-on experience with ARM-based SoC architectures, AMBA protocols (AXI/AHB/APB), and system-level interactions.\nProven ability to build reusable, scalable testbench architectures.\nSolid understanding of test planning, coverage-driven verification, and verification metrics.\nExperience with GLS, timing verification, and debug.\nKnowledge of power-aware verification (UPF/CPF).\nStrong scripting and automation skills (Python, Perl, Shell, Make, etc.).\nExposure to AI/ML techniques applied to verification (e.g., intelligent stimulus generation, failure triage, coverage optimization).\nExcellent problem-solving, debugging, and communication skills.\n#LI-RT1","description_format":"text","description_chars":2687,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Analog & Power Semiconductors","Machine Vision & 3D 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