{"id":924,"url":"https://alion.io/job/openai-senior-rtl-engineer-interconnect-design","title":"RTL Design Engineer – Interconnect & Network Datapath","company":{"id":2,"name":"OpenAI","domain":"openai.com","url":"https://alion.io/company/openai","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"B","score":78,"open_postings":196,"ghost_share":0,"stale_share":0.898,"repost_share":0,"time_to_fill_p50_days":51,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Francisco, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":225000,"max":445000,"currency":"USD","period":"year","gross":null,"usd_annual":445000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"HPC","optional":false},{"name":"InfiniBand","optional":false},{"name":"OpenAI","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-06-23T23:52:56Z","employer_posted_date":"2026-06-23","last_verified_at":"2026-10-17T19:04:36Z","board_verified":true,"closed_at":null,"days_open":115,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":115},"description":"About the Team\nOpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.\nAbout the Role\nWe are looking for a highly experienced, hands-on RTL engineer with deep packet-networking and interconnect expertise to own critical on- and off-chip communication components for our custom AI accelerator platform.\nYou will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting high-bandwidth compute, memory, and I/O subsystems, as well as purpose-built off-chip interfaces and protocols that enable custom computing at scale. The ideal candidate has recently owned production RTL for networking or packet-switched datapaths such as Ethernet switches, NICs, SmartNICs, network accelerators, RDMA/RoCE systems, NoCs, or custom scale-up/scale-out fabrics.\nThis is a senior engineering role with broad technical ownership and substantial direct RTL work. You will drive designs from requirements and performance analysis through microarchitecture, SystemVerilog implementation, verification closure, physical design convergence, silicon bring-up, and production readiness. You will also plan and oversee the work of junior engineers and help develop productive engineering relationships with external partners.\nIn this role, you will:\nOwn the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol adapters, arbiters, queues, schedulers, buffers, and traffic-management logic.\n\nDesign mechanisms for routing, arbitration, ordering, flow control, congestion management, quality of service, packet scheduling, buffering, and performance monitoring.\n\nDevelop on-chip and off-chip interfaces, protocol bridges, and custom networking protocols or protocol extensions for scale-up and scale-out systems.\n\nPerform substantial direct microarchitecture, SystemVerilog coding, simulation, and debug work.\n\nCollaborate with architecture and performance teams to analyze traffic patterns, identify bottlenecks, and optimize latency, bandwidth, fairness, and utilization under realistic workloads.\n\nWork with verification teams to develop coverage plans, assertions, stress scenarios, and debug strategies for highly concurrent packet and fabric behavior.\n\nPartner with physical design teams on floorplan-aware design, pipeline strategy, timing closure, power, area, and physical congestion.\n\nCollaborate with firmware, software, validation, and post-silicon teams through bring-up and production readiness.\n\nDrive third-party engagements involving networking, interface protocols, and silicon IP while maintaining design quality and execution accountability.\n\nProvide technical leadership through architecture and design reviews, documentation, mentoring, and reusable RTL methodologies.\n\nYou might thrive in this role if you have:\nExtensive industry experience with recent, hands-on ownership of complex networking, packet-processing, or packet-switched interconnect RTL.\n\nDemonstrated networking expertise in one or more of the following: Ethernet switching, NIC/SmartNIC/DPU datapaths, network accelerators, RDMA/RoCE, InfiniBand, traffic management, or custom scale-up/scale-out transports.\n\nDeep expertise in Verilog/SystemVerilog and the development of clean, parameterized, production-quality RTL.\n\nA strong record of owning major RTL blocks or SoC subsystems from requirements and microarchitecture through tape-out and silicon bring-up.\n\nExperience designing queues, arbiters, schedulers, buffers, routing logic, virtual channels, credit-based flow control, congestion management, quality of service, ordering, or deadlock-avoidance mechanisms.\n\nExperience with relevant on-chip, chip-to-chip, or host interfaces such as AXI, CHI, CXL, PCIe, or Ethernet, alongside deeper networking or packet-datapath expertise.\n\nExperience designing custom networking protocols, protocol extensions, or hardware datapaths for large-scale RDMA/RoCE, HPC, or AI systems.\n\nStrong familiarity with RTL development and signoff flows, including lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, and design-for-test considerations.\n\nExperience collaborating with architecture, verification, physical design, firmware, performance, and post-silicon teams to deliver complex silicon.\n\nStrong judgment when balancing performance, power, area, schedule, verification risk, and physical implementation constraints.\n\nThe ability to provide technical direction, mentor engineers, and drive alignment while remaining actively involved in RTL design and debugging.\n\nA passion for reducing complexity and improving engineering leverage through automation and pragmatic design.\n\nPreferred Qualifications\nExperience designing packet-switched interconnect or networking datapaths for AI accelerators, GPUs, CPUs, HPC systems, NICs/SmartNICs, switch ASICs, or large-scale datacenter silicon.\n\nExperience addressing virtualization, isolation, RAS, telemetry, security, or memory-consistency requirements within complex networking or interconnect subsystems.\n\nExperience with network or NoC performance modeling, traffic simulation, emulation, FPGA prototyping, or post-silicon traffic and performance analysis.\n\nExperience leading architecture or RTL delivery for first-generation networking or interconnect IP in rapidly evolving silicon programs.\n\nTo comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.\nAbout OpenAI\nOpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.\nWe are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.\nFor additional information, please see OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement.\nBackground checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.\nTo notify OpenAI that you believe this job posting is non-compliant, please submit a report through this form. No response will be provided to inquiries unrelated to job posting compliance.\nWe are committed to providing reasonable accommodations to applicants with disabilities, and requests can be made via this link.\nOpenAI Global Applicant Privacy Policy\nAt OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. 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