{"id":1062067,"url":"https://alion.io/job/oq-technology-fpga-engineer","title":"FPGA Engineer","company":{"id":687894,"name":"OQ TECHNOLOGY","domain":"oqtec.com","url":"https://alion.io/company/oqtec","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Join","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"remote","remote_scope":"stated_regions","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Luxembourg City, Luxembourg"],"countries":["LU"],"hiring_countries":["DE","FR","GB","AT","BE","BG","HR","CZ","DK","FI","HU","IE","IT","NL","NO","PL","RO","ES","SE","CH","EE","GR","IS","LV","LI","LT","LU","MT","PT","SK","SI"],"hiring_countries_total":31,"salary":null,"salary_estimate":{"min_usd":83000,"max_usd":193000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":536},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Linux","optional":false},{"name":"MATLAB","optional":false},{"name":"RTOS","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Vitis","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"Bash","optional":true},{"name":"Cadence Genus","optional":true},{"name":"Git","optional":true},{"name":"Python","optional":true},{"name":"Siemens ModelSim","optional":true},{"name":"Siemens QuestaSim","optional":true},{"name":"Synopsys Design Compiler","optional":true},{"name":"UVVM","optional":true},{"name":"Vitis HLS","optional":true}],"status":"live","first_seen_at":"2026-08-04T08:54:58Z","employer_posted_date":"2026-08-04","last_verified_at":"2026-09-30T10:13:31Z","board_verified":true,"closed_at":null,"days_open":57,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":57},"description":"With our groundbreaking satellite 5G constellation, OQ Technology is a global leader in IoT communication connectivity and associated services. We are a venture capital-backed company with a successful track record of satellite launches and are the first company in the world to disrupt the telecommunications industry by merging cellular 5G with satellites.\nOur technology has massive implications for the Oil & Gas, Maritime, Industry 4.0, and Transport sectors, particularly in the management and tracking of assets in remote and rural areas and in extending 5G coverage through non-terrestrial networks.\nAs our wireless technologies continue to evolve and earn multiple awards, with funding for the next phase secured and strong commercial traction demonstrated, we are now looking to onboard a talented FPGA Engineer to join our engineering team in Luxembourg and contribute to the continued growth and success of our organization.\nThe role sits within the payload and radio development group and carries hands-on responsibility for the design, implementation, integration, and verification of FPGA firmware for satellite and telecommunications applications. The engineer will work within a multidisciplinary team spanning hardware, software, RF, and systems engineering, contributing across the development lifecycle from RTL implementation and simulation through hardware bring-up and laboratory validation.\nExperience in space or telecommunications applications is preferred. Candidates with a strong FPGA implementation background from adjacent domains - defence, radar, wireless infrastructure, or high-speed digital systems will be considered where the core FPGA skills are well evidenced.\nTasks\nThe engineer will be responsible for FPGA firmware design and verification across digital signal processing, baseband, and high-speed interface functions for satellite payload and telecommunications applications. Typical tasks include:\nArchitect, design, and implement FPGA firmware in VHDL and/or Verilog/SystemVerilog for digital signal processing, high-speed interfaces, and control logic. \nOptimise FPGA resource utilisation, timing closure, and power efficiency on Xilinx/AMD Zynq, Zynq UltraScale+, Kintex, Virtex, and Artix device families using Vivado and Vitis toolchains. \nImplement DSP algorithms in FPGA fabric, including filtering, modulation and demodulation, FFT, decimation, and baseband processing functions, using RTL or HLS as appropriate. \nImplement high-speed communication interfaces including AXI4, AXI-Stream, AXI-Lite, JESD204B, PCIe, Ethernet, SPI, I²C, UART, and DDR4. \nDevelop testbenches and simulation environments to verify RTL behaviour against functional specifications prior to hardware integration. \nExecute functional and regression simulation using industry-standard tools, documenting results against defined acceptance criteria. \nWork with embedded processors including ARM Cortex-A53, ARM Cortex-R5, and MicroBlaze, integrating FPGA logic with Linux, RTOS, or bare-metal software environments. \nPerform FPGA bring-up, hardware debugging, and validation using Vivado Logic Analyser, Integrated Logic Analyser, oscilloscopes, and spectrum analysers. \nImplement telecommunication algorithms from MATLAB or C/C++ reference models and verify bit-accurate correspondence between reference and hardware outputs. \nInterface with RF front-end hardware to resolve firmware-hardware integration issues and ensure consistency of signal interfaces. \nPrototype solutions using SDR platforms such as Xilinx RFSoC, USRP, or Analog Devices evaluation hardware to support proof-of-concept demonstrations. \nContribute to the maintenance and improvement of the internal test laboratory capability. \nProduce and maintain firmware implementation documentation, test plans, test reports, and configuration records. \nContribute to design reviews, test readiness reviews, and technical progress reviews. \nWork within a multidisciplinary team spanning software, firmware, hardware, and RF engineering disciplines. \nReport regularly on implementation and test progress to the responsible senior engineer or project manager.\nRequirements\nMandatory:\nBachelor’s degree in Electronic Engineering, Electrical Engineering, Computer Engineering, Telecommunications Engineering, or a closely related discipline. \nMinimum three years of demonstrable hands-on experience in FPGA firmware development, including RTL design, simulation, synthesis, and hardware bring-up. \nProficiency in VHDL and/or Verilog/SystemVerilog for RTL design and functional simulation. \nDemonstrated experience with Xilinx/AMD FPGA device families and Vivado or Vitis toolchains, including constraint-driven implementation and timing closure. \nWorking knowledge of FPGA architecture including DSP slices, block RAM, clock management resources, and high-speed serial transceivers. \nExperience developing testbenches and executing structured simulation and verification campaigns. \nExperience performing hardware bring-up and laboratory testing of FPGA-based systems. \nFamiliarity with embedded processor integration within FPGA environments, including AXI-based hardware-software interfaces. \nAbility to implement and verify algorithms from MATLAB or C/C++ reference models. \nProficiency in spoken and written English. \nResident in Europe with valid right to work.\nDesirable:\nExperience in satellite telecommunications applications, including familiarity with CCSDS, DVB-S2/S2X, DVB-RCS2, or NTN waveform standards. \nExperience with SDR platform development, including integration of baseband firmware with RF front-end hardware on platforms such as Xilinx RFSoC, USRP, or Analog Devices ADRV900x/AD936x-based systems. \nExperience with Intel/Altera FPGA device families and Quartus Prime toolchain. \nExperience with High-Level Synthesis tools including Vivado HLS or Vitis HLS. \nExperience with embedded Linux integration on Zynq or Zynq UltraScale+ platforms, including Yocto build environment and kernel driver development. \nFamiliarity with ASIC-oriented RTL design practices, including synthesis to standard cell libraries, static timing analysis, DFT insertion, or power analysis using tools such as Synopsys Design Compiler or Cadence Genus. \nExposure to radiation-tolerant or space-grade FPGA design constraints and associated verification requirements. \nExperience with wireless or telecommunications PHY layer implementation, including digital signal processing for modulation, demodulation, synchronisation, or channel estimation. \nExperience contributing to technical documentation, design reviews, or technical proposals in an engineering programme context. \nScripting experience in Python, TCL, or Bash for build automation, test scripting, or tool integration.\nSoftware, Hardware & Platform Skills:\nVHDL, Verilog/SystemVerilog, MATLAB, C/C++, Python. \nXilinx/AMD Vivado, Vitis, ISE; Intel/Altera Quartus Prime. \nXilinx/AMD device families: Zynq, Zynq UltraScale+, Kintex, Virtex, Artix, RFSoC, Versal. \nSDR platforms: Xilinx RFSoC, NI USRP, Analog Devices ADALM-PLUTO, ADRV9002/ADRV9009 evaluation platforms, GNU Radio. \nHigh-speed interfaces: AXI4, AXI-Stream, JESD204B, PCIe, Ethernet, DDR4, SPI, I²C, UART, SpaceWire. \nSimulation and verification: ModelSim, QuestaSim, UVVM, or equivalent HDL simulation tools. \nLaboratory test equipment: oscilloscope, spectrum analyser, network analyser, logic analyser, ILA. \nVersion control: Git or equivalent. \nOperating environment: Linux.\nAdditional Information:\nAs part of the recruitment process, candidates may be required to provide a criminal record certificate issued within the last three (3) months.\nBenefits\nEnjoy a 50% income tax exemption on your salary - an exceptional incentive for top talent relocating to Luxembourg, subject to eligibility conditions.\nFlexibility to work remotely one day per week. \nOpportunity to work on flagship EU space mission projects.\nA dynamic, high-growth environment with career development opportunities.\nRegular company events and team activities.","description_format":"text","description_chars":8033,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":["Company events"],"hiring_locations":[{"name":"Germany","iso":"DE","kind":"region"},{"name":"France","iso":"FR","kind":"region"},{"name":"United Kingdom","iso":"GB","kind":"region"},{"name":"Austria","iso":"AT","kind":"region"},{"name":"Belgium","iso":"BE","kind":"region"},{"name":"Bulgaria","iso":"BG","kind":"region"},{"name":"Croatia","iso":"HR","kind":"region"},{"name":"Czech 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