{"id":2553101,"url":"https://alion.io/job/ovt-analog-design-engineer-4","title":"Analog Design Engineer","company":{"id":4417366,"name":"OmniVision","domain":"ovt.com","url":"https://alion.io/company/ovt-2","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jobvite","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":156853,"max":160000,"currency":"USD","period":"year","gross":null,"usd_annual":160000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence AFS","optional":false},{"name":"Cadence Virtuoso","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens ModelSim","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-14T18:28:03Z","employer_posted_date":"2026-10-14","last_verified_at":"2026-10-16T09:47:27Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Description\nConduct end-to-end design and development of advanced CMOS Image Sensor (CIS) technologies with a focus on transistor-level design, simulation, and verification of analog circuits using Cadence Virtuoso. \nDesign analog building blocks such as Analog Static RAM (ASRAM), ensuring support for complex readout formats including Dual Conversion Gain (DCG), Correlated Double Sampling (CDS), Correlated Multiple Sampling (CMS), and 4c2p. \nPerform complete schematic design flow, closely collaborate with layout engineers on device matching, symmetry, shielding, and routing for optimal noise performance and area efficiency. \nCarry out comprehensive post-layout verification, including Parasitic Extraction (PEX), Design Rule Check (DRC), Layout vs. Schematic (LVS), and Physical Electrical Rule Check (PERC) using Calibre.\nConduct system-level analog simulation and CIS signal chain verification to ensure correct signal propagation from pixel through the entire analog front-end to digital input interface.\nExecute extensive process, voltage and temperature (PVT) and Monte Carlo simulations to evaluate functional robustness, and performance margins. \nPerform IR drop analysis and power integrity verification to ensure reliable power delivery and layout feasibility.\nUtilize Analog FastSPICE (AFS), Empyrean ALPS, and NanoSpice for block-level and full-chain validation under realistic operating scenarios.\nDevelop and maintain automation scripts in Python and Perl to streamline simulation flow, including netlist generation, corner sweeping, batch result parsing, and yield analysis. Build scalable toolchains to support multi-corner, multi-mode simulations and regression testing, enhancing design turnaround and validation coverage.\nCollaborate with cross-functional teams with digital design, verification, process, and test to define analog-digital interface specifications, establish timing constraints, support readout calibration algorithms, and debug post-silicon performance issues. \nParticipate in design reviews, tapeout signoff, and lab characterization, contributing to silicon bring-up and performance optimization.\nRequirements:\nMaster’s degree in Electrical Engineering, Computer Engineering, or a related field with advanced-level courses work in Analog Integrated Circuit, CMOS Circuit Design, RF Circuits and Systems Design, VLSI system design, and VLSI Signal Processing.\nMust possess the following skills:\nAnalog circuits using MOS models,\nOperational amplifier and current mirror design,\nNoise analysis and feedback system,\nEvaluation of offset distortion and nonlinearity,\nFunctional verification using ModelSim,\nStatic timing analysis, power and area estimation,\nStandard-cell based logic and physical synthesis,\nHardware scheduling and retiming,\nNumber representation and digital arithmetic,\nFull analog IC design flow,\nPost-tapeout chip testing and validation,\nVLSI circuit and system design using Verilog,\nArchitecture design space exploration,\nSpectrum Analyzer.\nAnnual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.","description_format":"text","description_chars":3240,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-14T18:28:03Z"}],"visa":[],"liveness":{"score":99,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.993,"p_room":1,"age_days":1,"expected_fill_days":29,"reasons":["conf:1","wave","velocity","win:early"],"computed_at":"2026-10-16T05:45:00Z"},"pay":{"stated_usd_annual":160000,"is_top_pay":false},"html_url":"https://alion.io/job/ovt-analog-design-engineer-4","json_url":"https://alion.io/job/ovt-analog-design-engineer-4.json","meta":{"generated_at":"2026-10-16T12:04:41Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":11157,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-17T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4417366},"rest":"https://alion.io/mcp/rest/get_company?id=4417366"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fovt-analog-design-engineer-4"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fovt-analog-design-engineer-4"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fovt-analog-design-engineer-4"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ovt-analog-design-engineer-4\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fovt-analog-design-engineer-4"}]}