{"id":2553088,"url":"https://alion.io/job/ovt-digital-design-engineer","title":"Digital Design Engineer","company":{"id":4417366,"name":"OVT","domain":"ovt.wpengine.com","url":"https://alion.io/company/ovt-2","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jobvite","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Irvine, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":110600,"max":140000,"currency":"USD","period":"year","gross":null,"usd_annual":140000},"salary_estimate":null,"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-14T18:28:03Z","employer_posted_date":"2026-10-14","last_verified_at":"2026-10-15T06:13:04Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Description\nKey Responsibilities:\nDesign and implement sensor timing control logic and contribute to ISP system-level integration\nParticipate in chip-level architecture definition, including analog interfaces, control logic, image data processing pipelines, and power/performance/area (PPA) trade-offs\nIntegrate and validate ISP data paths based on PRD, design specifications, and overall SoC architecture\nCollaborate closely with CIS project leads and sensor digital/analog engineers for system integration and validation\nWork with physical design teams on floor planning, timing closure, and DFT implementation\nPerform full-chip integration and verification\nSupport chip bring-up, validation, and silicon debugging\nCollaborate with algorithm and application engineers on image tuning, optimization, and qualification\nSupport silicon validation, debugging, and image quality tuning through production readiness\nMinimum Qualifications\nBachelor’s degree in Electrical Engineering, Computer Engineering, or a closely related field, or equivalent practical experience\nAt least 2 years of hands-on experience designing RTL digital logic using Verilog/System Verilog, or equivalent industry experience\nProficiency with scripting languages such as Python or Perl to support design, verification, and automation workflows\nExperience analyzing and optimizing area, power, and performance (PPA) trade-offs in digital designs\nPreferred Qualifications\nMaster’s degree or PhD in Electrical Engineering, Computer Engineering, or a related discipline\nStrong background in image sensor and camera system design or integration\nExperience with high-speed MIPI interfaces (e.g., CSI-2 / D-PHY / C-PHY)\nPractical experience with Image Signal Processing (ISP) architectures and pipelines\nAnnual base salary for this role in California, US is expected to be between $110,600 - $140,000. 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