Sr. Product Engineer
Confirmed on the employer's own hiring board on Oct 15, 2026. First seen by Alion on Oct 14, 2026.
Description
Design a characterization/testing plan and work with R&D teams and manufacturing engineers to resolve various technical issues to meet performance requirements; participate in product definition and provide DFM inputs; work in close collaboration with silicon foundry, imager characterization and pixel design; interact with foundry fab in improving all silicon process, color, and package issues; improve product yield and performance by process optimization and layout design update; analyze yield and drive corrective actions for yield improvements; drive characterization to finalize the product datasheet; work with pixel design group to design the most sophisticated and optimized pixel layout; work with characterization team to analyze and debug pixel device circuit and various image related issues; ramp up for image sensors and ASIC devices; coordinate with company's fab to drive semiconductor processing tool vendors to optimize processes, including raw material vendor, IMP tool vendor and photo resist vendor etc.; set up new tape out product process flows, inline handbooks, JDV check etc.; work with testing engineers to develop, verify and release testing program at CP or FT.Program coding, such as python, to improve work efficiency in data analysis.
Requirements:
Master’s degree or foreign equivalent degree in Materials Science & Engineering, Physics, or related fields.
Require two years of experience in process integration.
Require experience/skills of:
- Analyze the correlation among Yield/Defect/Inline/Reliability and reduce lost.
- Assess CMOS Imaging Process to maximize the production capacity in Fab.
- Construct multiple work systems with IT to reduce workload.
- Release CMOS Imaging Process proposals to deduct the expense of material and improve the yield of wafer edge.
- Conduct a course to enhance colleagues' vigilance against product defect disasters.
- Implement customers’ IP design into new node and perform trial run in Fab.
- Forecast yield precisely and estimate the target in next season.
- Plan the process/testing priority of the product to trace issues during the mass production.
- Ensure the quality of the wafers by the strict management from wafer-start to fab-out.
Annual base salary for this role in California, US is expected to be between $131,706 - $135,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.