{"id":2553126,"url":"https://alion.io/job/ovt-sr-product-engineer","title":"Sr. Product Engineer","company":{"id":4417366,"name":"OVT","domain":"ovt.wpengine.com","url":"https://alion.io/company/ovt-2","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jobvite","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":131706,"max":135000,"currency":"USD","period":"year","gross":null,"usd_annual":135000},"salary_estimate":null,"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-10-14T18:28:03Z","employer_posted_date":"2026-10-14","last_verified_at":"2026-10-15T10:30:39Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Description\nDesign a characterization/testing plan and work with R&D teams and manufacturing engineers to resolve various technical issues to meet performance requirements; participate in product definition and provide DFM inputs; work in close collaboration with silicon foundry, imager characterization and pixel design; interact with foundry fab in improving all silicon process, color, and package issues; improve product yield and performance by process optimization and layout design update; analyze yield and drive corrective actions for yield improvements; drive characterization to finalize the product datasheet; work with pixel design group to design the most sophisticated and optimized pixel layout; work with characterization team to analyze and debug pixel device circuit and various image related issues; ramp up for image sensors and ASIC devices; coordinate with company's fab to drive semiconductor processing tool vendors to optimize processes, including raw material vendor, IMP tool vendor and photo resist vendor etc.; set up new tape out product process flows, inline handbooks, JDV check etc.; work with testing engineers to develop, verify and release testing program at CP or FT.Program coding, such as python, to improve work efficiency in data analysis.\nRequirements:\nMaster’s degree or foreign equivalent degree in Materials Science & Engineering, Physics, or related fields.\nRequire two years of experience in process integration.\nRequire experience/skills of:\nAnalyze the correlation among Yield/Defect/Inline/Reliability and reduce lost.\nAssess CMOS Imaging Process to maximize the production capacity in Fab.\nConstruct multiple work systems with IT to reduce workload. \nRelease CMOS Imaging Process proposals to deduct the expense of material and improve the yield of wafer edge.\nConduct a course to enhance colleagues' vigilance against product defect disasters.\nImplement customers’ IP design into new node and perform trial run in Fab.\nForecast yield precisely and estimate the target in next season.\nPlan the process/testing priority of the product to trace issues during the mass production.\nEnsure the quality of the wafers by the strict management from wafer-start to fab-out.\nAnnual base salary for this role in California, US is expected to be between $131,706 - $135,000. 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