{"id":2553099,"url":"https://alion.io/job/ovt-staffsr-staff-npu-design-engineer","title":"(Staff/Sr. Staff) NPU Design Engineer","company":{"id":4417366,"name":"OmniVision","domain":"ovt.com","url":"https://alion.io/company/ovt-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jobvite","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Singapore"],"countries":["SG"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":73000,"max_usd":144000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":13},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"CNN","optional":true}],"status":"live","first_seen_at":"2026-10-14T18:28:03Z","employer_posted_date":"2026-10-14","last_verified_at":"2026-10-30T21:02:39Z","board_verified":true,"closed_at":null,"days_open":16,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":16},"description":"Description\nResponsibilities:\nDevelop design requirements for an NPU based on system level specifications.\nBeing part of modelling the performance of the NPU module and its data transaction throughput.\nMicroarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.\nUnderstanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)\nEstimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.\nOptimizing micro-architecture design for low power and area is required.\nWork closely with verification engineers to ensure comprehensive testing and debug any issues.\nSupport integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.\nCollaborate with software teams to assist in compiler and toolchain development and their debugging.\nProduce clear and concise design documentation.\nRequirements:\n8+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.\nAt least one cycle of NPU design completion experience is required.\nHands on experience in digital design is a must.\nPreferably has led a team of at least 3 to 4 people in the past at the capacity of a design lead.\nExperience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.\nExperience in synthesis, with analysis of power, timing and area.\nDisciplined, quality-minded, and highly driven for excellence.\nExcellent team player and good communication skills.\nMSEE/BSEE in Electrical Engineering or Computer Engineering.\nUnderstanding of convolution operator and number system is required.\nCandidates with relevant experience would be offered as Senior, taking on higher responsibilities.\nExperience in UVM verification methodology is a plus.\nA plus to have SoC design experience.\nExperience with optimizing micro-architectures for low-power and low-area is a plus.\nKnowledge in deep learning algorithms such as CNN / Transformer is a plus.\nExperience with past design experience with NPU / GPU / DSP design is a plus.\nExperience with ARM or RISC-V processor systems is a plus.\nBeing passionate and proficient at general programming is a plus.","description_format":"text","description_chars":2248,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":3,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-14T18:28:03Z"}],"visa":[],"liveness":{"score":85,"band":"hot","label":"Hiring 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