{"id":3724312,"url":"https://alion.io/job/pebble-square-inc-analog-design-engineer-adcdac","title":"Analog Design Engineer (ADC/DAC)","company":{"id":2676531,"name":"Pebble Square","domain":"pebble-square.com","url":"https://alion.io/company/pebble-square","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ninehire","truth_index":{"grade":"B","score":73,"open_postings":9,"ghost_share":0.444,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-11-09T06:03:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Seongnam, South Korea"],"countries":["KR"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Synopsys HSPICE","optional":false},{"name":"MATLAB","optional":true},{"name":"Python","optional":true},{"name":"Siemens Calibre","optional":true}],"status":"live","first_seen_at":"2026-07-16T02:22:31Z","employer_posted_date":"2026-08-19","last_verified_at":"2026-11-09T15:39:22Z","board_verified":true,"closed_at":null,"days_open":116,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":116},"description":"About the Role\n당사는 Flash 또는 memory-based readout 회로에 적용되는 고성능 ADC/DAC 및 핵심 아날로그/혼성신호 블록을 설계할 경력직 아날로그 회로설계 엔지니어를 찾고 있습니다.\n본 포지션은 SAR ADC, Single-Slope ADC, DAC/Ramp Generator, Comparator, OP Amp, Bandgap Reference(BGR) 등 ADC/DAC 및 관련 Analog IP의 아키텍처 정의, 트랜지스터 레벨 회로설계, 시뮬레이션, layout 협업, post-layout 검증, silicon characterization 업무를 담당합니다.\nFlash, Digital, Layout, Design Verification, Silicon Bring-up 팀과 협업하여 memory readout 회로의 성능, 전력, noise, sampling speed, SNR 등 핵심 성능 지표를 달성하는 역할을 수행합니다.\nKey Responsibilities\nADC/DAC 및 Analog IP 설계: Flash 또는 memory-based readout 회로에 적용되는 ADC/DAC 및 관련 Analog IP의 아키텍처 정의, 트랜지스터 레벨 회로설계 및 시뮬레이션을 수행합니다.\nData Converter 설계: SAR ADC, Single-Slope ADC, DAC, Ramp Generator 등 data converter 구조를 설계하고 성능을 최적화합니다.\nBlock-Level Analog 설계: Comparator, OP Amp, Bandgap Reference(BGR), reference/bias circuit, ADC calibration 관련 회로 등 핵심 아날로그 블록을 설계하고 검증합니다.\nAMS Simulation 및 검증: PVT corner, transient, AC/DC, noise, linearity, mismatch, Monte Carlo, post-layout simulation 등을 통해 회로 성능과 설계 리스크를 검증합니다.\nLayout 협업 및 Post-layout 검증: Layout Engineer와 협업하여 device matching, symmetry, shielding, parasitic mitigation, noise coupling 방지 등 custom analog layout guideline을 제공하고 PEX 기반 post-layout 성능 검증을 수행합니다.\nSilicon Characterization 및 Debug: Tape-out 이후 test chip 또는 silicon 측정 결과를 분석하고, SNR, SNDR, ENOB, sampling speed, offset, gain error, INL/DNL, power consumption 등 ADC/DAC 성능 지표를 검증·최적화합니다.\nCross-functional Collaboration: Flash, Digital, Layout, Design Verification, Physical Design, Silicon Bring-up 팀과 협업하여 mixed-signal integration, calibration, interface 검증, silicon debug 업무를 수행합니다.\n문서화 및 설계 리뷰: 설계 사양서, 시뮬레이션 결과, layout guideline, 검증 보고서, silicon characterization report를 작성하고 설계 리뷰에 참여합니다.\nQualifications\n경력: Analog/Mixed-Signal IC 설계 분야에서 5년 이상의 실무 경험을 보유하신 분\n(관련 전공의 석사 졸업자의 경우 관련 분야 2년 이상의 실무 경험 보유자)\nAnalog/Mixed-Signal IC 설계 경험: CMOS 기반 아날로그/혼성신호 IC의 transistor-level 설계 및 시뮬레이션 경험을 보유하신 분\nADC/DAC 또는 Analog IP 경험: SAR ADC, Single-Slope ADC, DAC, Ramp Generator, Comparator, OP Amp, BGR, reference/bias circuit 등 ADC/DAC 또는 관련 Analog IP 설계 경험을 보유하신 분\nEDA Tool 활용 역량: Cadence Virtuoso, Spectre, HSPICE 또는 이에 준하는 analog IC 설계/시뮬레이션 tool 사용 경험을 보유하신 분\nSimulation 역량: PVT corner, noise, mismatch, Monte Carlo, post-layout simulation 등 회로 검증 경험을 보유하신 분\nLayout 이해도: device matching, parasitic effect, shielding, symmetry, noise isolation 등 custom analog layout 고려사항에 대한 이해를 보유하신 분\n학력: 전기전자공학, 반도체공학 또는 관련 전공 학사 이상 학위 보유자\n소프트 스킬: 원활한 커뮤니케이션 역량, 부서 간 협업 능력 그리고 ADC/DAC, Memory Readout, Analog/Mixed-Signal IC 기술에 대한 높은 관심과 이해를 갖춘 분\nPreferred Qualifications\nSAR ADC, Single-Slope ADC, DAC, Ramp Generator 등 Data Converter 설계 경험 보유자\nComparator, OP Amp, Bandgap Reference(BGR), Reference/Bias Circuit 등 아날로그 IP 설계 경험 보유자\nFlash, Memory Readout Circuit, Computing-in-Memory(CIM) 관련 회로 설계 경험 보유자\nADC/DAC Calibration, Offset/Gain Correction, Trimming 등 보정 회로 설계 경험 보유자\nTape-out, Test Chip, Silicon Validation, Post-Silicon Characterization 경험 보유자\nCalibre DRC/LVS/PEX, Fast-SPICE Simulator 등 EDA Tool 활용 경험 보유자\nPVT, Noise, Mismatch, Monte Carlo, Post-layout Simulation 등 회로 검증 경험 보유자\nMATLAB, Python, C 기반 분석·자동화 경험 보유자\nAnalog/Mixed-Signal IC 설계 관련 석사 또는 박사 학위 보유자\n전형절차\n서류전형 - 1차 실무 면접 - 2차 컬처핏 면접 - 입사\n*영문 입사지원서로 제출하여 주시기 바랍니다.\nAbout the Role\nWe are looking for an experienced Analog Circuit Design Engineer to design high-performance ADC/DAC and key analog/mixed-signal blocks for Flash or memory-based readout circuits.\nThis position will be responsible for architecture definition, transistor-level circuit design, simulation, layout collaboration, post-layout verification, and silicon characterization of ADC/DAC and related Analog IPs, including SAR ADC, Single-Slope ADC, DAC/Ramp Generator, Comparator, OP Amp, and Bandgap Reference (BGR).\nYou will work closely with Flash, Digital, Layout, Design Verification, and Silicon Bring-up teams to achieve key performance metrics for memory readout circuits, including performance, power, noise, sampling speed, and SNR.\nKey Responsibilities\nADC/DAC and Analog IP Design: Define the architecture, perform transistor-level circuit design, and run simulations for ADC/DAC and related Analog IPs used in Flash or memory-based readout circuits.\nData Converter Design: Design and optimize data converter architectures such as SAR ADC, Single-Slope ADC, DAC, and Ramp Generator.\nBlock-Level Analog Design: Design and verify key analog blocks, including Comparator, OP Amp, Bandgap Reference (BGR), reference/bias circuits, and ADC calibration-related circuits.\nAMS Simulation and Verification: Verify circuit performance and design risks through PVT corner, transient, AC/DC, noise, linearity, mismatch, Monte Carlo, and post-layout simulations.\nLayout Collaboration and Post-Layout Verification: Work closely with Layout Engineers to provide custom analog layout guidelines, including device matching, symmetry, shielding, parasitic mitigation, and noise coupling prevention, and perform PEX-based post-layout performance verification.\nSilicon Characterization and Debug: Analyze test chip or silicon measurement results after tape-out, and verify and optimize ADC/DAC performance metrics such as SNR, SNDR, ENOB, sampling speed, offset, gain error, INL/DNL, and power consumption.\nCross-functional Collaboration: Collaborate with Flash, Digital, Layout, Design Verification, Physical Design, and Silicon Bring-up teams on mixed-signal integration, calibration, interface verification, and silicon debug activities.\nDocumentation and Design Review: Prepare design specifications, simulation results, layout guidelines, verification reports, and silicon characterization reports, and participate in design reviews.\nQualifications\nExperience: 5+ years of hands-on experience in Analog/Mixed-Signal IC design.\n(Candidates with a master’s degree in a related field and 3+ years of relevant hands-on experience may also be considered.)\nEducation: Bachelor’s degree or higher in Electrical Engineering, Semiconductor Engineering, or a related field.\nAnalog/Mixed-Signal IC Design Experience: Hands-on experience in transistor-level design and simulation of CMOS-based analog/mixed-signal ICs.\nADC/DAC or Analog IP Experience: Experience designing ADC/DAC or related Analog IPs, such as SAR ADC, Single-Slope ADC, DAC, Ramp Generator, Comparator, OP Amp, BGR, and reference/bias circuits.\nEDA Tool Proficiency: Experience using analog IC design and simulation tools such as Cadence Virtuoso, Spectre, HSPICE, or equivalent tools.\nSimulation Skills: Experience with circuit verification, including PVT corner, noise, mismatch, Monte Carlo, and post-layout simulations.\nLayout Understanding: Understanding of custom analog layout considerations, including device matching, parasitic effects, shielding, symmetry, and noise isolation.\nSoft Skills: Excellent communication skills, cross-functional collaboration skills, and a strong interest and understanding of ADC/DAC, memory readout, and analog/mixed-signal IC technologies.\nPreferred Qualifications\nExperience designing data converters such as SAR ADC, Single-Slope ADC, DAC, and Ramp Generator.\nExperience designing Analog IPs such as Comparator, OP Amp, Bandgap Reference (BGR), and reference/bias circuits.Experience designing circuits related to Flash, memory readout circuits, or Computing-in-Memory (CIM).\nExperience designing calibration circuits such as ADC/DAC calibration, offset/gain correction, and trimming.\nExperience with tape-out, test chips, silicon validation, or post-silicon characterization.\nExperience using EDA tools such as Calibre DRC/LVS/PEX and Fast-SPICE simulators.\nExperience with circuit verification, including PVT, noise, mismatch, Monte Carlo, and post-layout simulations.\nExperience with analysis and automation using MATLAB, Python, or C.\nMaster’s or Ph.D. degree related to Analog/Mixed-Signal IC design.","description_format":"text","description_chars":7849,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","LLM & Generative AI","Machine Learning"],"lifecycle":[{"event":"open","at":"2026-11-04T04:30:48Z"}],"visa":[],"liveness":{"score":8,"band":"cold","label":"Long shot","p_open":1,"p_active":0.3,"p_room":0.28,"age_days":116,"expected_fill_days":29,"reasons":["conf:0","ghost","win:tail","crowd:"],"computed_at":"2026-11-09T06:03:00Z"},"pay":null,"html_url":"https://alion.io/job/pebble-square-inc-analog-design-engineer-adcdac","json_url":"https://alion.io/job/pebble-square-inc-analog-design-engineer-adcdac.json","meta":{"generated_at":"2026-11-09T20:59:07Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":8842,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-10T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":2676531},"rest":"https://alion.io/mcp/rest/get_company?id=2676531"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fpebble-square-inc-analog-design-engineer-adcdac"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fpebble-square-inc-analog-design-engineer-adcdac"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fpebble-square-inc-analog-design-engineer-adcdac"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/pebble-square-inc-analog-design-engineer-adcdac\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fpebble-square-inc-analog-design-engineer-adcdac"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3724312}},{"tool":"search_jobs","arguments":{"company":"pebble-square.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3724312},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}