{"id":714654,"url":"https://alion.io/job/persimmons-silicon-design-engineer","title":"Silicon Design Engineer","company":{"id":685393,"name":"Persimmons","domain":"persimmons.ai","url":"https://alion.io/company/persimmons","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workable","truth_index":{"grade":"B","score":81,"open_postings":4,"ghost_share":0,"stale_share":0.75,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":116000,"max_usd":261000,"period":"year","method":"role_country_seniority_unknown","sample_n":3123},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-13T00:00:00Z","employer_posted_date":"2026-10-13","last_verified_at":"2026-10-29T00:17:11Z","board_verified":true,"closed_at":null,"days_open":16,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":15},"description":"Who we are:\nPersimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, We’re on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn’t imagined yet.\nWhy join us:\nWe’re growing fast and looking for bold thinkers, builders, and curious problem-solvers who want to push the limits of AI hardware and software. If you’re ready to join a world-class team and play a critical role in making a global impact - we want to talk to you.\nWhat you'll do:\nAs a Persimmons Silicon Design Engineer, you will be responsible for high quality RTL drops to our PD Partners of next-generation AI silicon. Your primary duties and responsibilities include:\nOwn RTL-to-PD handoff flows to PD Partners, including synthesis, timing constraints, upf and static checks. Ensuring designs meet quality, performance, power & area targets.\nLead unit level design execution & verification planning. Collaborate with architecture, software, and design teams to develop MAS, execution & test plans that ensures we meet SoC specifications.\nDrive timing closure by authoring precise timing constraints from RTL understanding, running static timing analysis & resolving setup violations across complex multi-corner environments.\nExecute floorplanning and physical implementation using Cadence/Synopsys tools, making informed decisions on macro placement & tool options to optimize PPA.\nBuild and maintain scripted, automated design flows that streamline synthesis, analysis, and sign-off processes-leveraging AI agents and modern automation tools to accelerate iteration and reduce manual overhead.\nCollaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend handoffs, enforce quality checks, and ensure seamless integration across the design hierarchy.\nContribute to advanced post DV design activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and DFT scan and MBIST integration as scope demands.\nRequirements\nWhat You Bring To The Table:\nEducational Foundation: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.\nProven Experience: 3+ years of hands-on RTL-to-PD implementation experience, with demonstrated success taking designs from synthesis through tapeout on real silicon.\nExperience with MAS & test plan development, test implementation, and complex debugging across diverse IP blocks, SoCs, and system-level designs.\nStrong skills in SystemVerilog, Verification methodology, and C/C++ embedded code for processors validation.\nTechnical Mastery: Proficiency in SystemVerilog/Verilog and deep familiarity with Cadence and/or Synopsys synthesis and physical implementation toolchains, including all associated quality and sign-off checks.\nSpecialized Expertise: Strong command of static timing analysis and the ability to write timing constraints from scratch based on RTL-level design understanding.\nFlow Innovation: Experience developing and maintaining scripted, automated design flows; exposure to AI-assisted automation tools is a strong plus.\nDemonstrated fluency with modern AI tools and workflows (e.g., leveraging AI assistants for research, analysis, or productivity).\nBenefits\nCompetitive salary and benefits package\nFlexible PTO\n401k\nPlease note: Our organization does not accept unsolicited candidate submissions from external recruiters or agencies. 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