{"id":1980959,"url":"https://alion.io/job/phizenix-asic-design-engineer","title":"ASIC Design Engineer","company":{"id":19836,"name":"PHIZENIX","domain":"phizenix.com","url":"https://alion.io/company/phizenix","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Conformal","optional":false},{"name":"Embedded C","optional":false},{"name":"C","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-07-20T19:21:11Z","employer_posted_date":"2026-10-06","last_verified_at":"2026-10-12T06:00:01Z","board_verified":true,"closed_at":null,"days_open":83,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":83},"description":"Job description :\nRole Overview\nWe are seeking an ASIC Design Engineer to own digital design, integration, and bring-up for production-grade high-speed interconnect silicon. You will translate micro-architecture into clean, high-quality RTL and drive it through synthesis and timing closure. Just as important, the ideal candidate leverages strong firmware coding experience to drive pre-silicon simulation, develop bare-metal diagnostics, and ensure seamless hardware-software integration-for example, writing firmware on an embedded RISC CPU IP to control on-chip analog hardware blocks and low-speed control/calibration loops for optical components. Strong digital ASIC fundamentals, paired with the ability to debug complex designs in emulation and on silicon, round out the profile.\nKey Responsibilities\nDevelop micro-architecture and author high-quality, synthesizable RTL following best-in-class coding methods and design-for-verification / design-for-test practices.\nWrite firmware and bare-metal diagnostics on embedded RISC CPU IP to configure and control on-chip analog blocks and low-speed control/calibration loops for optical components.\nDrive pre-silicon simulation and hardware-software co-verification, validating firmware against RTL well ahead of tape-out.\nIntegrate processor subsystems-including licensed CPU IP-AMBA fabrics, and serial/interconnect interfaces (e.g., PCIe, UCIe) into the SoC/ASIC.\nDrive the full implementation flow: synthesis, timing constraints (SDC), timing closure, and equivalence checking (Formality / Conformal), with clean Lint / CDC / RDC signoff.\nBuild and run emulation environments; lead silicon bring-up sequences and post-silicon debug, root-causing and resolving issues on hardware.\nProvide responsive support-triaging design problems and delivering timely solutions-and collaborate with analog/mixed-signal, DSP, verification, and physical-design teams.\nRequired Qualifications\nEducation & Experience\nB.S. or M.S. in Electrical/Electronics or Computer Engineering (or related), with relevant digital ASIC design experience.\nDemonstrated experience taking digital designs from RTL through synthesis, timing closure, and silicon bring-up.\nCore Technical Skills\nStrong fundamentals in digital ASIC design, micro-architecture, and best RTL coding methods.\nFirmware / embedded C development, including bare-metal programming on an on-chip RISC CPU IP (e.g., RISC-V or Arm) to drive analog blocks and low-speed loops.\nKnowledge of AMBA and serial protocols, processors, and silicon bring-up sequences.\nStrong design, emulation, and silicon debug skills, with proven hardware-software integration experience.\nExpertise in synthesis, constraints, timing closure, and equivalence checks (Formality / Conformal).\nExperience with Lint / CDC / RDC tools.\nProfessional Skills\nCustomer-support orientation and excellent communication and oratory skills.\nPreferred Qualifications\nFamiliarity with interconnect protocols such as PCIe (Gen5/6/7) and UCIe.\nExperience integrating vendor CPU IP and developing the associated firmware, drivers, and diagnostics.\nHigh-speed wireline / SerDes-based SoC experience; UPF low-power design, DFT, and scan/ATPG flows.\nScripting proficiency (Python, Tcl)","description_format":"text","description_chars":3231,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Management Consulting","AI Consulting & Integration"],"lifecycle":[{"event":"open","at":"2026-10-06T23:30:41Z"}],"visa":[],"liveness":{"score":14,"band":"cold","label":"Long shot","p_open":1,"p_active":0.408,"p_room":0.35,"age_days":83,"expected_fill_days":41,"reasons":["conf:0","velocity","win:tail"],"computed_at":"2026-10-12T06:55:09Z"},"pay":null,"html_url":"https://alion.io/job/phizenix-asic-design-engineer","json_url":"https://alion.io/job/phizenix-asic-design-engineer.json","meta":{"generated_at":"2026-10-12T07:26:11Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":11917,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":19836},"rest":"https://alion.io/mcp/rest/get_company?id=19836"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fphizenix-asic-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fphizenix-asic-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fphizenix-asic-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/phizenix-asic-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fphizenix-asic-design-engineer"}]}