{"id":2376383,"url":"https://alion.io/job/phizenix-system-advanced-packaging-design-lead","title":"System & Advanced Packaging Design Lead","company":{"id":19836,"name":"PHIZENIX","domain":"phizenix.com","url":"https://alion.io/company/phizenix","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":180000,"max":200000,"currency":"USD","period":"year","gross":null,"usd_annual":200000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys SIwave","optional":false},{"name":"Cadence Allegro","optional":false}],"status":"live","first_seen_at":"2026-10-12T14:54:29Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-14T19:32:49Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Role Overview\nWe are seeking an Advanced 2.5D/3D/Chiplet packaging Lead, who will be directing Signal Integrity for Package, PCB and System design for Copper Interconnects beyond 200G, Work on enabling advanced packaging for Driver, TIA & Optics for AI Scale up engine including SI/ PI, Reliability, Thermals and HVM; Also drive Micro-LED packaging and Heterogeneous package development. Good understanding of OSAT ecosystem and drive the development of complete solutions for data-centers\nKey Responsibilities\nTechnical Leadership & Execution\nOwn package, PCB, and system-level signal integrity architecture for 200G+/lane copper interconnects (C2M, C2C, and cable assemblies) - from channel budgeting and topology definition through post-layout signoff and correlation with silicon measurements.\nDrive 2.5D/3D and heterogeneous package development for co-packaged driver, TIA, and optical engines, including substrate architecture, interposer/bridge evaluation, and die-package co-design with the SerDes and analog design teams.\nLead micro-LED and photonic packaging development: optical coupling and alignment strategy, hermeticity and reliability, and thermal co-design with the optical engine.\nDefine and manage the OSAT and substrate supplier strategy - technology selection, DFM reviews, JEDEC qualification, yield ramp, and HVM readiness.\nOwn package-level power integrity and thermal strategy: PDN targets, decoupling plans, lid/TIM selection, and clear signoff criteria across programs.\nCoordinate cross-functional execution across silicon design, product/test engineering, systems hardware, and manufacturing partners; run design reviews and manage schedule and risk.\nHands-On Design\nPersonally drive substrate stackup definition, ballmap/pinmap optimization, and high-density breakout and escape routing studies for high-speed designs.\nPerform 3D EM extraction and channel simulation (HFSS/Q3D, ADS or equivalent), S-parameter quality checks, and COM/IL/RL budgeting against IEEE 802.3 and OIF-CEI specifications.\nBuild and correlate PDN and thermal models spanning die, package, and board.\nLead lab characterization: VNA/TDR measurements, BER and eye-margin testing, model-to-measurement correlation, and failure analysis support.\nAuthor package design guidelines, review checklists, and reference collateral used across product programs.\nRequired Qualifications\nEducation & Experience\nPh.D. in Electrical Engineering (or related) with 5+ years, OR M.S. with 8+ years of Advanced package development in high volume.\nProven experience leading teams to successful execution, with multiple products delivered in advanced CMOS nodes.\nCore Technical Skills\nDeep SI/PI expertise for multi-GHz serial links: 112G/224G PAM4 channel design, COM analysis, crosstalk and mode-conversion control, and connector/cable interfaces.\nAdvanced packaging depth: FCBGA, RDL/fan-out, 2.5D interposers and silicon bridges, substrate design rules, and materials selection.\nFluency with industry tools: HFSS, Q3D, SIwave/PowerSI, ADS channel simulation, Cadence APD/Allegro (or equivalent), and thermal tools such as Icepak or FloTHERM.\nReliability and qualification: JEDEC standards, moisture sensitivity, thermo-mechanical stress, and warpage/coplanarity management for large-body packages.\nWorking knowledge of optics packaging: VCSEL/PD or silicon-photonics co-packaging, fiber and lens coupling, and active alignment concepts.\nLeadership & Program Skills\nTrack record leading small internal teams and external partners (OSATs, substrate vendors, contract labs) through complete product cycles into volume production.\nStrong program discipline: schedule and risk management, structured design reviews, and clear documentation in a fast-moving environment.\nExcellent cross-functional communication with silicon, systems, and executive stakeholders; comfortable presenting technical trade-offs to customers and partners.\nPreferred Qualifications\nExperience with co-packaged optics, linear-drive optics, or active copper/electrical cable (ACC/AEC) products.\nMicro-LED, VCSEL, or photonic device packaging experience.\nFamiliarity with UCIe and chiplet/die-to-die interconnect packaging.\nHands-on HVM ramp experience at leading OSATs (ASE, Amkor, JCET, or similar).\nPrior startup experience or comfort operating with broad scope under resource constraints.\nCalifornia Pay Range\n$180,000—$200,000 USD","description_format":"text","description_chars":4387,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"phd","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Packaging & Labeling","Management Consulting","AI Consulting & Integration"],"lifecycle":[{"event":"open","at":"2026-10-12T18:37:57Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":1,"expected_fill_days":62,"reasons":["conf:3","win:early"],"computed_at":"2026-10-14T06:34:16Z"},"pay":{"stated_usd_annual":200000,"is_top_pay":false},"html_url":"https://alion.io/job/phizenix-system-advanced-packaging-design-lead","json_url":"https://alion.io/job/phizenix-system-advanced-packaging-design-lead.json","meta":{"generated_at":"2026-10-14T21:23:32Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":28593,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-15T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":19836},"rest":"https://alion.io/mcp/rest/get_company?id=19836"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fphizenix-system-advanced-packaging-design-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fphizenix-system-advanced-packaging-design-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fphizenix-system-advanced-packaging-design-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/phizenix-system-advanced-packaging-design-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fphizenix-system-advanced-packaging-design-lead"}]}