{"id":1521546,"url":"https://alion.io/job/positron-ai-asic-design-engineer-2","title":"ASIC Design Engineer","company":{"id":63106,"name":"Positron AI","domain":"positron.ai","url":"https://alion.io/company/positron-ai","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"inferred","locations":[],"countries":[],"hiring_countries":["US","CA"],"hiring_countries_total":2,"salary":{"min":150000,"max":200000,"currency":"USD","period":"year","gross":null,"usd_annual":200000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AWS Lambda","optional":false},{"name":"Groq","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"AWS","optional":true},{"name":"Cocotb","optional":true},{"name":"Formal Verification","optional":true},{"name":"UVM","optional":true}],"status":"closed","first_seen_at":"2026-09-29T11:00:47Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-10-05T13:21:00Z","board_verified":false,"closed_at":"2026-10-05T13:21:00Z","days_open":6,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":6},"description":"About Positron AI\nPositron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep running into two walls at inference time: memory bandwidth and chip-to-chip networking. We designed our architecture to break through both. Our first-generation Atlas systems are deploying in Oracle Cloud Infrastructure. Asimov, our first custom ASIC, takes that architecture to silicon. In simulations, Asimov delivers several times more tokens per dollar and tokens per watt than leading GPUs, at a fraction of the power. Paired in our Titan system, Asimov is built to serve models beyond 16 trillion parameters. In September 2026, we raised $875 million at a $5 billion valuation. NEA led the round, joined by Atreides Management, Valor Equity Partners, and others, to bring Asimov and Titan to market. Our team includes engineers from Groq, Lambda, NVIDIA, Meta, F5, and many other industry leaders.\nRole Overview\nAs an ASIC Design Engineer, you will help design, implement, and deliver IP blocks and subsystems for Positron.ai's inference ASICs/SoCs. Working under the guidance of senior engineers, you will write and verify SystemVerilog RTL, take ownership of well-scoped blocks, and learn the full front-end flow from microarchitecture through RTL signoff. You'll collaborate closely with architecture, verification, and physical design teams, building deep hands-on experience with high-performance silicon while growing toward greater technical ownership.\nKey Responsibilities\nRTL Design & Implementation:\nImplement clean, parameterized SystemVerilog RTL for assigned blocks based on microarchitecture specs developed with senior engineers.\nContribute to microarchitecture documentation and help define block-level interfaces.\nAdd embedded assertions and follow team guidelines for clocking, resets, and power intent.\nFront-End Flows & Quality:\nRun and debug lint, CDC/RDC, and synthesis checks on your blocks, and resolve issues with support from the team.\nHelp with timing analysis and work with PD on block-level timing fixes.\nTrack and report PPA metrics for your blocks, and propose optimizations.\nInterface & Integration Work:\nSupport integration of standard interfaces and IP (e.g., AMBA AXI, DMA engines, memory controllers).\nLearn and apply protocol requirements for high-performance interconnects and memory interfaces.\nMethodology & Automation:\nFollow established coding guidelines, IP packaging standards, and signoff checklists.\nWrite and maintain scripts (Python/Tcl/Make) that improve design flows and team productivity.\nCross-Functional Collaboration:\nWork with Verification to review test plans, debug failures, and close coverage on your blocks.\nHelp correlate RTL behavior against architecture and performance models.\nTake part in bring-up and post-silicon debug activities as needed.\nLearning & Growth:\nTake part in design reviews, present your work, and incorporate feedback.\nBuild expertise in microarchitecture tradeoffs through mentorship from senior engineers.\nRequired Qualifications\nBS/MS in EE/CE (or related field) with 0-3 years of ASIC/SoC RTL design experience (internships and relevant graduate research count).\nSolid working knowledge of SystemVerilog/Verilog for synthesizable RTL design.\nUnderstanding of digital design fundamentals: clocking, resets, pipelining, FSMs, FIFOs, and clock domain crossing.\nExposure to front-end tools and flows (simulation, lint, synthesis, or STA) from industry or academic projects.\nFamiliarity with at least one of: AMBA AXI/AHB/APB, DDR/HBM, PCIe, cache/memory hierarchies, or datapath design.\nScripting ability in Python, Tcl, or similar.\nStrong problem-solving skills, eagerness to learn, and clear written and verbal communication.\nPreferred Qualifications\nCoursework, research, or project experience in computer architecture or AI/ML accelerator design (matrix/vector engines, systolic arrays).\nExperience writing SystemVerilog Assertions (SVA) or exposure to formal verification.\nFamiliarity with low-power design concepts (clock gating, power gating, UPF).\nExperience with cocotb or UVM testbenches.\nExposure to RISC-V, FPGA prototyping, or tapeout of a chip (including academic tapeouts).\nLeveling & Scope\nWhile this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a different level for the right candidate. This job description is a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience of the final hire.\nWhy Join Us?\nHelp shape the next generation of AI inference hardware alongside a high-caliber, collaborative team.\nGet hands-on ownership of real silicon blocks early in your career.\nLearn directly from experienced ASIC architects and designers.\nCompetitive salary + equity, comprehensive benefits, and flexible work environment.\nClear opportunities to grow your scope, skills, and influence as the company scales.\nCompensation and Benefits\nThe base salary range for this role is $150,000 - $200,000.\nThese figures represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits. At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose skills, experience, or qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity and individual impact.\nEqual Opportunity Employer. If you're excited about the role but don't meet every bullet, we'd still love to hear from you.","description_format":"text","description_chars":5830,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Flexible schedule"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"},{"name":"Canada","iso":"CA","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Servers & Data Center Hardware","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-30T12:03:16Z"},{"event":"close","at":"2026-10-05T13:21:00Z"}],"visa":[{"country":"CA","licensed_sponsor":true,"evidence":"Approved LMIA in the last two years","filings_12m":0,"filings_prev_12m":1,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":null,"cap_exempt":false,"checked_at":"2026-10-03T21:10:52+00:00","sources":["ESDC: employers issued a positive LMIA"],"filings_for_role_12m":0}],"liveness":null,"pay":{"stated_usd_annual":200000,"is_top_pay":true},"html_url":"https://alion.io/job/positron-ai-asic-design-engineer-2","json_url":"https://alion.io/job/positron-ai-asic-design-engineer-2.json","meta":{"generated_at":"2026-10-09T02:12:55Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":43,"day_limit":5000,"remaining_today":4957,"minute_limit":60,"resets_at":"2026-10-10T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":63106},"rest":"https://alion.io/mcp/rest/get_company?id=63106"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fpositron-ai-asic-design-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fpositron-ai-asic-design-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fpositron-ai-asic-design-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/positron-ai-asic-design-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fpositron-ai-asic-design-engineer-2"}]}