{"id":1171112,"url":"https://alion.io/job/positron-ai-asic-design-engineer-principal","title":"ASIC Design Engineer, Principal","company":{"id":63106,"name":"Positron AI","domain":"positron.ai","url":"https://alion.io/company/positron-ai","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":225000,"max":350000,"currency":"USD","period":"year","gross":null,"usd_annual":350000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Cocotb","optional":true},{"name":"Formal Verification","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-08-02T19:34:29Z","employer_posted_date":"2026-08-02","last_verified_at":"2026-10-21T19:37:00Z","board_verified":true,"closed_at":null,"days_open":80,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":80},"description":"About Positron AI\nPositron AI specializes in developing custom hardware systems to accelerate AI inference. These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt. Positron exists to create the world's best AI inference systems.\nRole Overview\nAs a Principal ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the microarchitecture from high-level concept through RTL signoff, collaborating across architecture, verification, and physical design to achieve ambitious PPA and schedule goals. In addition to hands-on SystemVerilog design, you will mentor junior engineers, influence methodology, and drive key architectural tradeoffs that impact silicon performance and efficiency.\nKey Responsibilities\nMicroarchitecture & RTL Leadership:\nDefine and document microarchitecture for complex IP blocks/subsystems.\nDeliver production-quality, parameterized SystemVerilog RTL with well-defined interfaces, power/clock intent, and embedded assertions.\nTechnical Ownership & Signoff:\nLead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with PD on floorplan and timing closure.\nOwn PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.\nAdvanced Interface & Memory Integration:\nArchitect and integrate high-performance interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and high-speed memory interfaces (HBM/DDR).\nEngage with IP vendors and internal stakeholders to ensure seamless integration.\nMethodology & Best Practices:\nDevelop and enforce coding guidelines, reusable IP packaging, and signoff checklists.\nContribute automation flows (Python/Tcl/Make/CI) to improve team efficiency.\nCross-Functional Collaboration:\nPartner closely with Verification to define test plans and reference models.\nWork with Architecture and Performance teams to correlate models against RTL.\nSupport bring-up, post-silicon debug, and customer engagements as required.\nMentorship & Technical Leadership:\nGuide junior engineers in design techniques, methodology, and problem-solving.\nLead design reviews, drive consensus on tradeoffs, and advocate for best-in-class solutions.\nRequired Qualifications\nBS/MS in EE/CE (or related) with 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon.\nProven track record of leading designs from spec → microarchitecture → RTL → signoff with strong PPA outcomes.\nDeep SystemVerilog RTL expertise, including clocking, resets, CDC/RDC handling, and protocol correctness.\nExtensive experience with front-end flows/tools (lint, CDC, synthesis/STA, DFT) using major EDA suites.\nHands-on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, high-throughput datapaths.\nStrong cross-functional communication skills, capable of leading technical discussions and producing clear specifications.\nPreferred Qualifications\nBackground in AI/ML accelerator design (matrix/vector engines, compression, NoC bandwidth planning).\nFormal verification/SVA expertise for property checking and design assertions.\nExperience with low-power design techniques (clock-/power-gating, UPF/CPF).\nCollaboration experience with cocotb/UVM for checkers and reference model co-development.\nFamiliarity with RISC-V subsystems, coherence protocols, or customer-owned tooling (COT) flows.\nLeveling & Scope\nWhile this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.\nWhy Join Us?\nShape the next generation of AI inference hardware with a high-caliber, collaborative team.\nTake technical ownership of critical silicon components that directly impact product success.\nCompetitive salary + equity, comprehensive benefits, and flexible work environment.\nOpportunities to innovate, lead, and grow your influence in a rapidly evolving space.\nCompensation and Benefits\nThe base salary range for this role is $225,000 - $350,000.\nPlease note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.\nAt Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.\nEqual Opportunity Employer. If you’re excited about the role but don’t meet every bullet, we’d still love to hear from you.","description_format":"text","description_chars":5149,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Equity","Flexible schedule"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Servers & Data Center Hardware","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-24T07:33:40Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 5","filings_12m":5,"filings_prev_12m":1,"green_card_filings_12m":0,"median_offered_wage_usd":300500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":2}],"liveness":{"score":39,"band":"fade","label":"Fading","p_open":1,"p_active":0.704,"p_room":0.55,"age_days":79,"expected_fill_days":63,"reasons":["conf:0","win:tail"],"computed_at":"2026-10-21T05:46:15Z"},"pay":{"stated_usd_annual":350000,"is_top_pay":true},"html_url":"https://alion.io/job/positron-ai-asic-design-engineer-principal","json_url":"https://alion.io/job/positron-ai-asic-design-engineer-principal.json","meta":{"generated_at":"2026-10-21T23:28:40Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":33460,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-22T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":63106},"rest":"https://alion.io/mcp/rest/get_company?id=63106"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fpositron-ai-asic-design-engineer-principal"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fpositron-ai-asic-design-engineer-principal"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fpositron-ai-asic-design-engineer-principal"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/positron-ai-asic-design-engineer-principal\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fpositron-ai-asic-design-engineer-principal"}]}