{"id":1521548,"url":"https://alion.io/job/positron-ai-asic-physical-design-engineer-dft-senior","title":"ASIC Physical Design Engineer - DFT, Senior","company":{"id":63106,"name":"Positron AI","domain":"positron.ai","url":"https://alion.io/company/positron-ai","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"posting_text","remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":[],"countries":[],"hiring_countries":["US"],"hiring_countries_total":1,"salary":{"min":200000,"max":300000,"currency":"USD","period":"year","gross":null,"usd_annual":300000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"AWS Lambda","optional":false},{"name":"Groq","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Tessent","optional":false},{"name":"Verilog","optional":false},{"name":"AWS","optional":true},{"name":"Cadence Palladium","optional":true},{"name":"Siemens Veloce","optional":true},{"name":"Synopsys ZeBu","optional":true}],"status":"live","first_seen_at":"2026-09-29T11:11:19Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-10-19T13:13:13Z","board_verified":true,"closed_at":null,"days_open":20,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":20},"description":"About Positron AI\nPositron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep running into two walls at inference time: memory bandwidth and chip-to-chip networking. We designed our architecture to break through both. Our first-generation Atlas systems are deploying in Oracle Cloud Infrastructure. Asimov, our first custom ASIC, takes that architecture to silicon. In simulations, Asimov delivers several times more tokens per dollar and tokens per watt than leading GPUs, at a fraction of the power. Paired in our Titan system, Asimov is built to serve models beyond 16 trillion parameters. In September 2026, we raised $875 million at a $5 billion valuation. NEA led the round, joined by Atreides Management, Valor Equity Partners, and others, to bring Asimov and Titan to market. Our team includes engineers from Groq, Lambda, NVIDIA, Meta, F5, and many other industry leaders.\nRole Overview\nAs Senior DFT Engineer, you'll own DFT implementation end-to-end: defining the DFT micro-architecture for our accelerators, developing and integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role from definition through tapeout and into first silicon, not a coordination role.\nKey Responsibilities\nHands-on DFT Implementation\nMicro-architect and implement DFT instrumentation logic, including scan insertion, compression, ATPG, memory BIST, boundary scan (IEEE 1149.x), IJTAG (IEEE 1687) infrastructure, and debug/observability features.\nIntegrate DFT IP into internally developed RTL, and evaluate and integrate DFT capabilities from third-party IP providers.\nWork directly in RTL, synthesis, and DFT tool flows.\nDrive Pre-Silicon DFT Verification\nDevelop comprehensive DFT verification plans and validate DFT functionality through simulation and gate-level verification.\nDrive stuck-at, transition, cell-aware, and power-aware ATPG strategies, ensuring DFx coverage targets are achieved before tapeout.\nPartner with Physical Design\nWork closely with backend implementation teams to ensure successful physical realization of the DFT architecture.\nGuide scan chain partitioning, compression planning, and test clock architecture.\nAddress power-aware test implementation, timing closure considerations, and test mode integration.\nCross-Functional Execution\nPartner closely with RTL design, design verification, physical design, package and test engineering, firmware, system software, and silicon validation to ensure DFT solutions are correct, compliant, complete, and consistent through silicon bring-up.\nAI-Enabled Engineering\nLeverage modern AI tools to improve engineering productivity, including automated review of DFT reports, ATPG and coverage analysis, regression triage, documentation generation, workflow automation, and agentic engineering assistants.\nRequired Qualifications\nA BS, MS, or PhD in Electrical Engineering or Computer Engineering.\n8+ years of ASIC development experience.\nExtensive hands-on DFT implementation experience on complex SoCs, with multiple successful production tapeouts.\nDeep understanding of scan architectures and their implementation, including ATPG, memory BIST (including repair), boundary scan, IJTAG, EDT, various fault models, and structural coverage analysis.\nHands-on experience with Siemens Tessent DFT solutions (SSN, EDT, MBIST, RTLpro, Scanpro, Tessent Diagnosis) is required.\nStrong RTL design skills using Verilog/SystemVerilog.\nPractical experience with synthesis and gate-level verification.\nStrong scripting ability in Python, Tcl, Perl, or similar languages.\nExcellent debugging skills across RTL, netlists, and silicon failure analysis.\nA demonstrated ability to drive technical execution across cross-functional engineering teams.\nPreferred Qualifications\nExperience with high-performance AI accelerators, GPUs, CPUs, networking ASICs, PCIe, HBM, LPDDR, or chiplet architectures.\nExposure to high-speed SerDes and advanced process nodes (5nm and below).\nBackground in low-power design, yield enhancement methodologies, and manufacturing test optimization.\nHands-on experience with silicon bring-up, failure analysis, and post-silicon debug.\nA solid grasp of secure manufacturing and DFT, including the interaction between secure boot, hardware root of trust, scan access control, fuse programming, key management, and production test.\nExperience architecting in-system debug and observability infrastructure (trace, event logging, test registers, scan visibility) that accelerates emulation and first-silicon bring-up.\nFamiliarity with emulation and pre-silicon validation platforms such as Palladium, ZeBu, Veloce, or FPGA prototyping to validate DFT features before tapeout.\nLeveling & Scope\nWhile this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.\nWhy Join Us?\nOwn DFT for a purpose-built AI inference accelerator from architecture definition through first silicon, with your decisions shaping Asimov and every generation that follows.\nJoin a small, senior hardware team where your work directly determines silicon quality, yield, and time to market for frontier AI workloads.\nCompensation & Benefits\nThe base salary range for this role is $200,000 - $300,000.\nPlease note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.\nAt Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.\nBenefits & Perks\nWe want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.\nHealth and wellness\nFully company-paid medical, dental, and vision insurance for you and your dependents\nCompany-paid life and disability coverage, with voluntary options to add more\nSupplemental hospital, critical illness, and accident coverage available\nTime off and flexibility\nUnlimited paid time off; we encourage everyone to truly unplug and recharge\n13 paid company holidays\nRemote-first culture with a company-provided computer and home office setup\nCompensation and future\nCompetitive salary and equity\n401(k) with company matching, eligible from day one\nVisa Support\nThis position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.\nEqual Opportunity Employer. If you're excited about the role but don't meet every bullet, we'd still love to hear from you.","description_format":"text","description_chars":7479,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Home office","Vision insurance"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Servers & Data Center Hardware","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-30T12:03:16Z"}],"visa":[{"country":"CA","licensed_sponsor":true,"evidence":"Approved LMIA in the last two years","filings_12m":0,"filings_prev_12m":1,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":null,"cap_exempt":false,"checked_at":"2026-10-03T21:10:52+00:00","sources":["ESDC: employers issued a positive LMIA"],"filings_for_role_12m":0}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.857,"p_room":1,"age_days":19,"expected_fill_days":63,"reasons":["conf:0","win:early"],"computed_at":"2026-10-19T05:45:15Z"},"pay":{"stated_usd_annual":300000,"is_top_pay":true},"html_url":"https://alion.io/job/positron-ai-asic-physical-design-engineer-dft-senior","json_url":"https://alion.io/job/positron-ai-asic-physical-design-engineer-dft-senior.json","meta":{"generated_at":"2026-10-19T16:03:37Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":12122,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-20T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":63106},"rest":"https://alion.io/mcp/rest/get_company?id=63106"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fpositron-ai-asic-physical-design-engineer-dft-senior"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fpositron-ai-asic-physical-design-engineer-dft-senior"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fpositron-ai-asic-physical-design-engineer-dft-senior"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/positron-ai-asic-physical-design-engineer-dft-senior\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fpositron-ai-asic-physical-design-engineer-dft-senior"}]}