{"id":65293,"url":"https://alion.io/job/powerlatticeinc-senior-digital-design-engineer","title":"Senior Digital Design Engineer","company":{"id":10684,"name":"Powerlatticeinc","domain":"powerlatticeinc.com","url":"https://alion.io/company/powerlatticeinc","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Chandler, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":150000,"max":200000,"currency":"USD","period":"year","gross":null,"usd_annual":200000},"salary_estimate":null,"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-08-19T22:57:36Z","employer_posted_date":"2026-08-19","last_verified_at":"2026-11-04T00:38:34Z","board_verified":true,"closed_at":null,"days_open":76,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":76},"description":"Senior or Staff Digital Design Engineer\nReports To: Head of Engineering\nAbout Us\nPowerlattice is a well-funded semiconductor start-up company backed by leading Silicon Valley venture capital firms. We are developing groundbreaking chiplet power delivery technology that will transform how high-performance processors are powered, enabling the next generation of AI and advanced computing.\nAbout the Role\nWe are seeking an experienced and hands-on Senior Digital Design Engineer to contribute to the design and implementation of complex digital systems and SoC components. This role offers the opportunity to own significant functional blocks from microarchitecture through RTL development, integration, and implementation while collaborating closely with verification, physical design, and DFT teams.\nThe ideal candidate is passionate about digital design, enjoys solving challenging technical problems, and thrives in a collaborative startup environment where individual contributions have a direct impact on product success.\nKey Responsibilities\nDigital Design & RTL Development\nDevelop microarchitecture for assigned digital blocks and subsystems\n\nDesign, code, and maintain high-quality, synthesizable RTL\n\nEvaluate design tradeoffs involving performance, power, area (PPA), and testability\n\nParticipate in design reviews and incorporate feedback into RTL implementation\n\nIntegration & Implementation\nIntegrate RTL into larger subsystem and SoC environments\n\nSupport lint, CDC/RDC, synthesis, and design quality checks\n\nCollaborate with physical design teams to resolve implementation issues\n\nAssist with timing constraint development and timing closure activities\n\nSupport logic equivalence checking (LEC) and implementation debugging\n\nParticipate in functional and timing ECO development when required\n\nDesign Quality\nEnsure designs meet functional, timing, power, and DFT requirements\n\nSupport silicon bring-up, validation, and post-silicon debug activities\n\nAnalyze and resolve design issues throughout the development lifecycle\n\nCross-Functional Collaboration\nWork closely with verification, DFT, physical implementation, firmware, and systems teams\n\nPartner with architects and senior technical leaders to refine design requirements\n\nContribute to continuous improvement of design methodologies and development processes\n\nMentor junior engineers and share technical knowledge within the team (Staff level)\n\nQualifications\nThis is a Hybrid role requiring 3 days a week onsite at our HQ’s in Vancouver, WA (Greater Portland Area) or Chandler, AZ.While we are primarily seeking candidates in HQ-Vancouver and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline\n\n6+ years of digital IC design experience\n\nStrong hands-on RTL development experience using Verilog or SystemVerilog\n\nExperience designing digital blocks for complex SoCs or ASICs\n\nSolid understanding of:\nRTL design and microarchitecture\n\nSoC integration and standard on-chip interfaces\n\nClocking, resets, CDC/RDC methodologies\n\nSynthesis and physical implementation considerations\n\nTiming constraints (SDC) and timing closure\n\nExperience with industry-standard EDA tools (Synopsys and/or Cadence)\n\nStrong debugging, analytical, and problem-solving skills\n\nExcellent communication and collaboration skills\n\nPreferred\nExperience with DFT methodologies including scan insertion and MBIST\n\nExperience with logic equivalence checking (LEC)\n\nFamiliarity with static timing analysis (STA)\n\nExperience with UPF/CPF low-power methodologies\n\nExposure to advanced semiconductor process nodes\n\nExperience supporting silicon bring-up and post-silicon debug\n\nFormal verification experience is a plus\n\nCompensation & Benefits\nAnticipated annual base salary for Member of Technical Staff: $150,000 - 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