{"id":1148656,"url":"https://alion.io/job/powerlatticeinc-senior-or-staff-design-verification-engineer","title":"Senior or Staff Design Verification Engineer","company":{"id":10684,"name":"Powerlatticeinc","domain":"powerlatticeinc.com","url":"https://alion.io/company/powerlatticeinc","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Chandler, United States","Vancouver, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":160000,"max":190000,"currency":"USD","period":"year","gross":null,"usd_annual":190000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Formal Verification","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Unix","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-23T16:19:58Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-11-05T05:13:41Z","board_verified":true,"closed_at":null,"days_open":42,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":42},"description":"Design Verification Lead\nReports To: Head of Engineering\nAbout Us\nPowerlattice is a well-funded semiconductor start-up company backed by leading Silicon Valley venture capital firms. We are developing groundbreaking chiplet power delivery technology that will transform how high-performance processors are powered, enabling the next generation of AI and advanced computing.\nAbout the Role\nWe are seeking an experienced and hands-on Design Verification Lead to spearhead verification activities for complex SoC/IP designs, developing scalable SystemVerilog-based verification environments, verification strategies, reusable test infrastructure, and automated regression flows. This position drives functional verification from RTL through gate-level simulation, including coverage closure, assertions, timing verification, and debug. They will collaborate closely with RTL, analog, architecture, and silicon validation teams to identify and resolve design issues.\nKey Responsibilities\nLead verification planning and execution for complex digital and mixed-signal subsystems, including defining verification strategies, test scenarios, coverage goals, and signoff criteria.\n\nArchitect, develop, and maintain SystemVerilog-based verification environments and reusable verification infrastructure.\n\nDevelop directed, constrained-random, regression, and corner-case tests to verify functional requirements and design specifications.\n\nDevelop reusable verification components and protocol-based test infrastructure for I2C/I3C, SPI, JTAG, AMBA, and OBI interfaces.\n\nPerform and support Clock Domain Crossing (CDC) verification for async and sync clock-domain interfaces.\n\nDevelop and maintain UVM-based infrastructure and RAL models where applicable.\n\nDevelop checkers, scoreboards, reference models, assertions, and functional coverage to provide comprehensive verification of design behavior.\n\nPerform RTL and gate-level simulation, including SDF-annotated GLS, to identify functional, timing, initialization, reset, and connectivity issues.\n\nDevelop and optimize regression and GLS flows using Xcelium and VCS.\n\nAnalyze functional and code coverage and drive coverage closure by identifying verification gaps and developing targeted tests.\n\nDebug complex RTL, testbench, simulation, and gate-level failures using waveform and log analysis.\n\nWork closely with RTL designers, analog designers, architects, and silicon validation teams to reproduce issues, determine root cause, and drive resolution.\n\nReview specifications and RTL to identify corner cases, interface issues, reset/clocking problems, and potential functional gaps.\n\nTranslate silicon validation findings into simulation-based verification scenarios and regression tests.\n\nProvide technical leadership to a team of verification engineers. Mentor the team in verification methodologies, tools, and coverage improvements.\n\nQualifications\nThis is a Hybrid role requiring 3 days a week onsite at our HQ’s in Vancouver, WA (Greater Portland Area) or Chandler, AZ.While we are primarily seeking candidates in HQ-Vancouver and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.\nBachelor's or master's degree in electrical engineering, Computer Engineering, or related field\n\n10+ years of experience in digital verification of SoCs with proven ownership of subsystems or full-chip verification.\n\nSolid Understanding of:\nDigital design fundamentals, FSMs, CDC, RDC, mixed-signal subsystems, and SoC integration.\n\nIndustry-standard protocols including AMBA, I²C, I3C, SPI, JTAG, and OBI.\n\nStrong Expertise in:\nVerilog, SystemVerilog, UVM and class-based verification methodologies.\n\nConstrained-random, coverage-driven verification, regression automation, and verification signoff.\n\nSystemVerilog Assertions (SVA), formal verification techniques.\n\nPython, Perl, and UNIX/Linux shell scripting for automation.\n\nHands-on experience developing testbenches, drivers, monitors, scoreboards, assertions, and reusable verification IP.\n\nStrong analytical and problem-solving skills, with the ability to debug complex issues, communicate clearly, mentor engineers, lead technical initiatives, and cross-functional collaboration skills.\n\nExperience with industry-standard EDA tools (Synopsys, Cadence)\n\nPreferred Qualifications\nWorking knowledge of PMIC architectures and power management principles.\n\nExperience with formal verification techniques\n\nCompensation & Benefits\nAnticipated annual base salary for Member of Technical Staff: $160k - $190k\nStock option grant\n\nComprehensive benefits package including health, dental, vision, and 401(k)","description_format":"text","description_chars":4631,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["AI Chips & Accelerators","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-09-23T16:41:26Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"Filed H-1B visas in the last two years","filings_12m":0,"filings_prev_12m":2,"green_card_filings_12m":0,"median_offered_wage_usd":null,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":0}],"liveness":{"score":39,"band":"fade","label":"Fading","p_open":1,"p_active":0.717,"p_room":0.55,"age_days":42,"expected_fill_days":38,"reasons":["conf:0","win:tail"],"computed_at":"2026-11-05T05:54:30Z"},"pay":{"stated_usd_annual":190000,"is_top_pay":false},"html_url":"https://alion.io/job/powerlatticeinc-senior-or-staff-design-verification-engineer","json_url":"https://alion.io/job/powerlatticeinc-senior-or-staff-design-verification-engineer.json","meta":{"generated_at":"2026-11-05T06:49:04Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":8505,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-06T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":10684},"rest":"https://alion.io/mcp/rest/get_company?id=10684"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fpowerlatticeinc-senior-or-staff-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fpowerlatticeinc-senior-or-staff-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fpowerlatticeinc-senior-or-staff-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/powerlatticeinc-senior-or-staff-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fpowerlatticeinc-senior-or-staff-design-verification-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":1148656}},{"tool":"search_jobs","arguments":{"company":"powerlatticeinc.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":1148656},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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