{"id":2450007,"url":"https://alion.io/job/proxelera-asic-dv-engineer","title":"ASIC DV Engineer","company":{"id":4429047,"name":"Proxelera","domain":"proxelera.com","url":"https://alion.io/company/proxelera","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Git","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-13T14:29:42Z","employer_posted_date":null,"last_verified_at":"2026-10-13T14:29:42Z","board_verified":false,"closed_at":null,"days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"Responsibilities:\nDefine and implement IP/SoC verification plans; build verification test benches to enable IP/sub-system/SoC level verification.\nDevelop functional tests based on verification test plan.\nDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.\nDebug, root-cause and resolve functional failures in the design, partnering with the Design team.\nPerform simulation-based testing, including functional, performance, and compliance testing.\nStay up-to-date with industry trends, standards, and best practices related to Networking.\nCollaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.\nDevelop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.\nMentor other engineers to drive and deliver high confidence verification for highly complex ASIC projects.\nRequirements:\nBachelor's degree in Electronics and Communication, Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.\nTrack record of first-pass success in ASIC development cycles.\nHands-on experience in Verilog, SystemVerilog, UVM, C/C, Python-based verification.\nExperience in IP/sub-system and/or SoC-level verification based on SystemVerilog UVM/OVM based methodologies.\nExperience in one or more of the following areas along with functional verification - Ethernet, 400G MAC, RDMA, TSO, LRO, PSP, ROCE (RDMA over Converged Ethernet), Congestion Control, etc.\nExperience with Design verification of Data-center applications like Video, AI/ML and Networking designs.\nExperience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.\nExperience in IP, cluster, and SoC-level verification in both RTL and gate-level setup.\nProficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments.\nExperience using analytical skills to craft novel solutions to tackle industry-level complex designs.\nDemonstrated experience with effective collaboration with cross-functional teams preferred.\nQualifications:\nExperience in development of UVM-based verification environments from scratch.\nExperience with development of fully automated flows and scripts for data exploration, analysis and performance verification.\nExperience with IP or integration verification of high-speed interfaces like Ethernet, PCIe, DDR, HBM.\nExperience with verification of ARM/RISC-V based sub-systems or SoCs.\nExperience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.\nExperience with revision control systems like Mercurial(Hg), Git or SVN.\nExperience with simulators and waveform debugging tools.\nExperience working across and building relationships with cross-functional design, model and emulation teams.\nNote:\nEthernet MAC verification, preferably RDMA knowledge.\nPCIe verification at SoC levels, preferably good exposure to TL. Pure PL knowledge is not OK. Pure DLL will not be shortlisted.\nSoC advanced verification, covering data path, UPF, performance verification, etc.","description_format":"text","description_chars":3275,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-13T14:29:42Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":20,"reasons":["seen:0","win:early"],"computed_at":"2026-10-14T02:25:47Z"},"pay":null,"html_url":"https://alion.io/job/proxelera-asic-dv-engineer","json_url":"https://alion.io/job/proxelera-asic-dv-engineer.json","meta":{"generated_at":"2026-10-14T02:25:47Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3680,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-15T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4429047},"rest":"https://alion.io/mcp/rest/get_company?id=4429047"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fproxelera-asic-dv-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fproxelera-asic-dv-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fproxelera-asic-dv-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/proxelera-asic-dv-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fproxelera-asic-dv-engineer"}]}