{"id":3258411,"url":"https://alion.io/job/qblox-snr-asic-design-engineer","title":"Snr ASIC Design Engineer","company":{"id":20997,"name":"Qblox","domain":"qblox.com","url":"https://alion.io/company/qblox","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Recruitee","truth_index":{"grade":"B","score":75,"open_postings":8,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Delft, Netherlands"],"countries":["NL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":70000,"max_usd":124000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":23},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Git","optional":false},{"name":"Python","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Agentic Workflows","optional":true},{"name":"AI Agents","optional":true},{"name":"MATLAB","optional":true},{"name":"Simulink","optional":true}],"status":"live","first_seen_at":"2026-06-25T12:29:42Z","employer_posted_date":"2026-06-25","last_verified_at":"2026-10-27T11:25:03Z","board_verified":true,"closed_at":null,"days_open":124,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":123},"description":"ASIC Design Engineer\nJoin us at Qblox as we revolutionize the landscape of quantum computing! Our technology is used around the globe by world-class research teams to build a cutting-edge control stack for industrial-scale quantum computers.\nOur distributed architecture allows parallel qubit readout, control, and intercommunication, ultimately interacting with physical qubits using high-frequency analog signals. Imagine what it takes to talk to 10,000 qubits with\nnanosecond-level synchronization and all-to-all connectivity, and you will understand the massive microarchitectural, design, and verification challenges we face as we transition our logic to dedicated silicon.\nWe foster a highly collaborative culture. You will take ownership of your projects, influence technical decisions, and work alongside analog/mixed-signal engineers, digital verification specialists, embedded software developers, and physicists.\nYour Role:\n Deconstruct Requirements & Design: Evaluate system requirements to\narchitect and implement robust, high-performance digital logic and IP\nblocks.\n Front-End Flow Ownership: Drive designs through the front-end ASIC\nflow, including RTL coding, linting, clock domain crossing (CDC)\nanalysis, and initial synthesis.\n Verification Collaboration: Write block-level self-checking testbenches\nand collaborate with the verification team to expand top-level UVM\nenvironments.\n Architectural Influence: Propose innovative changes to chip\narchitecture, power-saving strategies, and team methodologies.\n Cross-Functional Sparring: Act as a core technical sparring partner to a\ndiverse engineering team, continuously pushing for better ways of doing\nthings.\nRequirements\nEnough about us, what about you?\nTo thrive in this role, you should bring:\n Experience: 8+ years as a digital design engineer within an R&D or fabless ASIC environment, with a proven track record of successful silicon tape-outs/deliveries.\n RTL & Architecture: Deep fundamental knowledge of digital design, IP development, and RTL coding using VHDL and/or Verilog.\n EDA Tools & Flow: Strong experience with standard ASIC front-end EDA tools, processor/bus-system architectures (e.g., AMBA AXI/AHB protocols), and synthesis.\n Timing & Constraints: Solid understanding of static timing analysis (STA) constraints and timing closure methodologies.\n Mixed-Signal Familiarity: Understanding of analog/mixed-signal chips or IP (e.g., ADC/DAC interfaces, PLLs).\n Automation & Tools: Proficiency in scripting to automate design workflows (Python, Tcl, Shell) and version control (Git).\n Communication: Strong communication and collaboration skills.\nOptional Nice-to-Haves:\n Active experience with advanced verification frameworks (UVM).\n Prior experience with DFT (Design for Test) insertion, scan chains, and BIST.\n Experience with modelling and simulation in MATLAB / Simulink.\n Strong background in DSP and signal-processing filters.\n Familiarity with AI agentic workflows and automation within the design flow.\n Experience or a strong interest in the Quantum Computing field.","description_format":"text","description_chars":3081,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Hardware","Science & Engineering","Quantum Science & Computing","Quantum Computing Hardware"],"lifecycle":[{"event":"open","at":"2026-10-26T03:13:06Z"}],"visa":[],"liveness":{"score":9,"band":"cold","label":"Long shot","p_open":1,"p_active":0.335,"p_room":0.28,"age_days":123,"expected_fill_days":36,"reasons":["conf:3","win:tail","crowd:"],"computed_at":"2026-10-27T05:46:45Z"},"pay":null,"html_url":"https://alion.io/job/qblox-snr-asic-design-engineer","json_url":"https://alion.io/job/qblox-snr-asic-design-engineer.json","meta":{"generated_at":"2026-10-27T14:16:35Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":2692,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-28T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":20997},"rest":"https://alion.io/mcp/rest/get_company?id=20997"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fqblox-snr-asic-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fqblox-snr-asic-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fqblox-snr-asic-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/qblox-snr-asic-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fqblox-snr-asic-design-engineer"}]}