{"id":1181184,"url":"https://alion.io/job/qnulabs-fpga-and-rtl-design-engineer","title":"FPGA and RTL Design Engineer","company":{"id":2402086,"name":"QNu Labs","domain":"qnulabs.com","url":"https://alion.io/company/qnulabs","size_band":null,"is_staffing_agency":false,"is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":61000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":438},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Libero SoC","optional":false},{"name":"Siemens ModelSim","optional":false},{"name":"Siemens QuestaSim","optional":false},{"name":"Slack","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Xilinx Vivado","optional":false}],"status":"live","first_seen_at":"2026-09-24T14:12:42Z","employer_posted_date":null,"last_verified_at":"2026-09-24T14:12:42Z","board_verified":false,"closed_at":null,"days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"Requirements:\nExperience Required: 4 to 10 years of relevant FPGA design/verification experience.\nCandidates with strong hands-on FPGA development and debugging experience will be preferred.\nEducational Qualification: B. E. /B. Tech. or M. E. /M. Tech. in Electronics, Electronics and Communication, Electrical Engineering, VLSI Design, Embedded Systems, or related disciplines. Candidates from reputed engineering colleges and universities will be preferred.\nFPGA Design Engineer Requirements: Digital Design Fundamentals.\nStrong understanding of combinational and sequential logic, finite state machines (FSM), clock domain crossing (CDC), and synchronization techniques.\nTiming Analysis and Timing Closure: Setup Time, Hold Time, Recovery/Removal Checks, Slack Analysis, and Timing Violation Debugging. HDL Development: Strong Verilog/SystemVerilog and/or VHDL coding skills in RTL design, simulation, synthesis, and FPGA implementation protocols.\nKnowledge: UART, SPI, I2C, Ethernet, and PCIe. Added advantage: JESD204B/JESD204C, 10G/25G/40G/100G Ethernet MAC, MACsec, IPsec, high-speed serial interfaces, DSP, and signal processing.\nHands-on implementation of DSP algorithms in FPGA.\nExperience with filtering, FFT, digital signal processing pipelines, and optimization techniques is highly preferred for FPGA platforms.\nPractical experience with FPGA boards from Xilinx/AMD Microchip (Microsemi) and Intel (Altera).\nDebug and validation of FPGA bring-up and board-level debugging using ChipScope/ILA/SignalTap or equivalent debugging tools; hardware validation and troubleshooting.\nExperience using oscilloscopes, logic analyzers, and lab equipment and FPGA tools.\nExperience with any of the following tools: Vivado, Libero SoC, Quartus Prime, and ModelSim/QuestaSim.\nExperience with additional FPGA design tools will be an added advantage, including \"RTL design for low-power implementations\" and \"Knowledge in Partial reconfiguration, \" also in the list as an added advantage.","description_format":"text","description_chars":1984,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-09-24T14:12:42Z"}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":17,"reasons":["seen:0","win:early"],"computed_at":"2026-09-24T23:37:18Z"},"pay":null,"html_url":"https://alion.io/job/qnulabs-fpga-and-rtl-design-engineer","json_url":"https://alion.io/job/qnulabs-fpga-and-rtl-design-engineer.json","meta":{"generated_at":"2026-09-24T23:37:18Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1813,"day_limit":5000,"remaining_today":3187,"minute_limit":60,"resets_at":"2026-09-25T00:00:00Z"}}}