{"id":3903608,"url":"https://alion.io/job/qualcomm-advanced-package-design-engineer-principal-engineer","title":"Advanced Package Design Engineer – Principal Engineer","company":{"id":94,"name":"Qualcomm","domain":"qualcomm.com","url":"https://alion.io/company/qualcomm","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":70,"open_postings":1059,"ghost_share":0.25,"stale_share":0.146,"repost_share":0.449,"time_to_fill_p50_days":74,"computed_at":"2026-11-08T05:47:12Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Diego, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":210000,"max":315000,"currency":"USD","period":"year","gross":null,"usd_annual":315000},"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"ANSYS","optional":false},{"name":"HPC","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Cadence Allegro","optional":true},{"name":"Cadence Innovus","optional":true},{"name":"Cadence Integrity 3D-IC","optional":true},{"name":"Rest-Assured","optional":true},{"name":"Siemens Calibre","optional":true}],"status":"live","first_seen_at":"2026-10-29T00:00:00Z","employer_posted_date":"2026-11-06","last_verified_at":"2026-11-08T15:23:51Z","board_verified":true,"closed_at":null,"days_open":10,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":10},"description":"Company:\nQualcomm Technologies, Inc.Job Area:\nEngineering Group, Engineering Group > Packaging Engineering General Summary:\nWe are seeking a Principal Engineer to build and lead a 2.5D/3D Advanced Package Design team within CHS, supporting next-generation high-performance compute (HPC) and Datacenter products. This leader will own the development, deployment, and continuous improvement of scalable 2.5D/3D package design methodologies and flows, while also directing package architecture, design implementation, verification, and release for complex multi-die products.\nThe ideal candidate combines deep hands-on expertise in silicon-interposer, silicon-bridge, chiplet, HBM, and advanced substrate design with a proven record of developing engineering teams and production-quality design flows. The individual will evaluate and integrate industry EDA and foundry ecosystems, including standards and frameworks such as TSMC 3Dblox, and will partner with EDA vendors, foundries, OSATs, substrate suppliers, and internal engineering teams to establish robust, automated, and signoff-ready design solutions. This position requires strategic leadership, strong technical credibility, and the ability to translate emerging 2.5D/3D technologies into repeatable product execution.\nRole and Responsibilities:\nBuild, manage, mentor, and grow a high-performing 2.5D/3D advanced package design team consisting of package architects, physical-design engineers, methodology developers, CAD/automation engineers, and technical leads.\nOwn the strategy, roadmap, architecture, implementation, qualification, and deployment of end-to-end 2.5D/3D package design methodologies and flows for complex multi-die products.\nDevelop standardized, scalable, and reusable flows spanning early package planning, die/chiplet assembly definition, floorplanning, HBM and chiplet placement, bump and interface planning, interposer/bridge design, substrate design, package verification, signoff, tapeout, and release.\nLead implementation of 2.5D/3D packages using silicon interposers, silicon bridges, RDL interposers, advanced organic substrates, hybrid-bonded or vertically stacked die, HBM, and other emerging integration technologies.\nEvaluate and deploy foundry and EDA-vendor 3DIC solutions, including TSMC 3Dblox-compatible methodologies and interoperable implementation, analysis, verification, data-exchange, and signoff flows.\nDefine tool requirements and drive technical alignment with Cadence, Siemens EDA, Synopsys, Ansys, foundries, and other ecosystem partners to close capability gaps and improve design productivity, quality, and scalability.\nEstablish design-flow architecture, data models, interfaces, automation frameworks, configuration management, regression testing, release management, metrics, documentation, and user support for production package design.\nGuide package architecture and physical implementation across die/chiplet floorplanning, bump maps, HBM placement, die-to-die interfaces, package connectivity, routing topology, layer-stack optimization, power/ground distribution, board escape, and package-size optimization.\nDefine and govern package verification and signoff requirements, including connectivity, DRC, DFM, ERC, LVS-equivalent checks, assembly-rule compliance, package extraction, SI/PI, thermal, mechanical, reliability, and manufacturability reviews.\nPartner with silicon architecture, SoC physical design, DFT, SI/PI, thermal, mechanical, board, product engineering, manufacturing, and supply-chain teams to enable concurrent chip-package-board-system co-design.\nLead package design execution from feasibility through tapeout and production release; establish design reviews, technical checkpoints, risk tracking, escalation paths, and closure criteria across product programs.\nDrive methodology correlation and validation using representative test cases and product designs; ensure flow readiness, repeatability, traceability, and robustness before broad production adoption.\nEngage foundries, OSATs, substrate suppliers, and assembly partners to understand technology structures, process constraints, design rules, assembly requirements, test considerations, reliability risks, yield limiters, and production-readiness requirements.\nDevelop team capability plans, hiring profiles, training, succession plans, and technical career paths; coach senior engineers and establish subject-matter experts for key 2.5D/3D design domains.\nRepresent advanced package design in executive and program reviews, communicating roadmap decisions, architecture tradeoffs, methodology readiness, resource requirements, execution status, technical risks, and mitigation plans.\nSkills:\nThe Principal Engineer / Director brings deep 2.5D/3D technical expertise, design-methodology leadership, and demonstrated capability in the following areas:\nProven experience building and leading advanced package design, 3DIC methodology, package CAD, or physical-design teams, including hiring, mentoring, performance development, resource planning, and technical-lead development.\nDeep knowledge of 2.5D/3D integration technologies and structures, including silicon interposers, silicon bridges, RDL interposers, advanced organic substrates, HBM integration, chiplets, die stacking, micro-bumps, hybrid bonding, and package assembly.\nHands-on experience defining or deploying production 2.5D/3D design flows covering planning, implementation, verification, multi-physics analysis, design-data handoff, tapeout, and release.\nUnderstanding of industry 3DIC EDA ecosystems and foundry design enablement, including TSMC 3Dblox concepts, die/package assembly description, hierarchy, connectivity, constraints, design reuse, and cross-tool interoperability.\nExpertise with relevant package and 3DIC implementation environments from Cadence, Siemens EDA, Synopsys, or equivalent vendors; strong understanding of constraint management, database integration, automation, and signoff.\nExpert knowledge of advanced package physical design, including multi-die floorplanning, HBM placement, bump and interface planning, pinout optimization, high-density routing, interposer/bridge implementation, substrate stackup, power/ground planning, and board escape.\nStrong understanding of package-level SI/PI and electromagnetic effects for HBM, UCIe and other die-to-die interfaces, PCIe, DDR, high-speed SerDes, clocks, and high-current power delivery.\nWorking knowledge of package thermal-mechanical and reliability analysis, including warpage, die/interposer stress, material interactions, thermal interfaces, assembly process windows, failure mechanisms, and qualification requirements.\nExperience establishing DRC, DFM, ERC, connectivity, extraction, multi-physics, and release-signoff methodology using foundry, OSAT, substrate, and internal rules.\nStrong scripting and automation mindset, with experience developing maintainable flows using languages and environments such as Python, Tcl, Perl, shell, APIs, workflow orchestration, regression systems, and version control.\nAbility to assess EDA tool capability, benchmark competing solutions, define requirements, drive vendor roadmaps, resolve tool and methodology gaps, and establish production-support models.\nExcellent executive communication, technical decision-making, cross-functional influence, supplier engagement, and ability to lead globally distributed teams through complex, ambiguous engineering challenges.\nPreferred Qualifications:\nMaster's degree or Ph.D. in Electrical Engineering, Computer Engineering, Mechanical Engineering, Materials Science, or a related field, with 15+ years of semiconductor package design, 3DIC, physical-design methodology, or related experience; equivalent industry experience may be considered.\nDemonstrated record of building and managing a substantial advanced package design or methodology organization supporting multiple complex products and technology generations.\nProven ownership of production 2.5D/3D package design methodology and implementation for AI, HPC, Datacenter, accelerator, networking, or other high-performance multi-die products.\nDirect experience delivering packages that integrate compute SoCs or chiplets with HBM using silicon-interposer, silicon-bridge, RDL-interposer, or vertically integrated 3D solutions.\nExperience integrating foundry reference flows and assembly-description frameworks such as TSMC 3Dblox into internal design, analysis, verification, and tapeout environments.\nExtensive experience with industry-leading 2.5D/3D IC design, implementation, and verification environments, including Cadence Innovus, Integrity 3D-IC, Allegro Package Designer (APD), Virtuoso, Siemens Calibre 3DSTACK, and comparable Synopsys and Ansys 3DIC solutions.\nDemonstrated experience evaluating, integrating, and deploying multi-vendor EDA tools within foundry-qualified 2.5D/3D design flows, including familiarity with assembly-description and interoperability frameworks such as TSMC 3Dblox.\nExperience establishing cross-domain chip-package-board co-design and multi-physics workflows spanning electrical, thermal, mechanical, reliability, test, manufacturing, and system constraints.\nExperience working directly with leading foundries, OSATs, substrate suppliers, assembly partners, EDA vendors, and IP providers to evaluate, develop, validate, qualify, and ramp advanced packaging solutions.\nUnderstanding of HBM, UCIe or other die-to-die protocols, PCIe, DDR, and high-speed SerDes, including package architecture, layout, extraction, SI/PI, and verification implications.\nDemonstrated ability to define methodology roadmaps, prioritize investments, establish measurable design-flow quality and productivity targets, and drive deployment across a global engineering organization.\nDemonstrated innovation through advanced package solutions, EDA methodologies, automation, patents, publications, industry working groups, or standards engagement is highly desirable.\nMinimum Qualifications:\n• Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 8+ years of System/Package Design/Technology Engineering or related work experience.OR\nMaster's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 7+ years of System/Package Design/Technology Engineering or related work experience.\nOR\nPhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 6+ year of System/Package Design/Technology Engineering or related work experience.\nQualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\nTo all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. 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