ASIC / NoC Power and Solutions Senior/Staff Engineer - Qualcomm - Guyancourt, France

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General Summary:

The QITC mission is to develop and deploy custom-built interconnect hardware IPs, software tools, and exploration and verification methodologies so that SoC integration teams can quickly assemble SoCs with the desired Power Performance Area (PPA) characteristics.

To this end, QITC technology embraces the complete SoC infrastructure to provide increased SoC performance at minimal cost for integration. Our work is at the backbone of the SoC, interconnecting all major IP solutions.

You will join the Solutions Deployment Team with the mission of deploying and supporting the QITC NoC technology across all the SoCs of Qualcomm portfolio (Mobile, Automotive, Servers, IoT, Connectivity, etc..), with a particular focus on QITC’s power technologies.

This is a challenging position, working on most innovative technologies, surrounded by experts but also by users of our technology all over the world and from various teams (SoC Architecture, HW and SW Design, Verification, Debug, Post Silicon).

Responsibilities

In your role, you will:

• Collaborate regularly with highly skilled experts across different teams (Architecture, Hardware, software, verification, emulation, ...) to ensure our technology is used efficiently in Qualcomm SoCs
• Contribute to the definition of interconnect requirements and configuration in the various SoCs
• Provide support on power issues and technology of new QITC solutions and general technical support
• Help resolve NoC power micro-architecture and NoC power unit integration issues
• Participate in defining new or improved power architectures and power NoC units and be responsible for their validation in our technology
• Develop in-depth technical material and organize training for different teams worldwide

Skills/Experience

• Strong understanding of overall SoC development flow: SoC architecture, RTL design and verification, SoC performance and DDR memory channel, physical implementation, silicon debug.
• Good knowledge in system level features such as memory-mapping, MMUs, Quality of service, cache infrastructure, security schemes, etc..
• Knowledge of low-power techniques in SoCs and experience of resolving power-related issues.
• Strong analytical skills for debug in simulation , emulation or silicon bring-up environments.
• Understand interconnect protocols like AHB/AXI/ACE/ACE-Lite/CHI and NoC concepts.
• Ability to quickly react and adapt to changes.
• Excellent communication skills.

Minimum Qualifications

• Master’s degree in Microelectronics, Computer Science, or related field.
• Preferably 3-5 years of solid experience in design, architecture and/or application engineering in SoC/ASIC development cycle.
• Standard SoC knowledge: Multimedia Ips, GPU, multi-core CPU architecture, Processors, Caches, memory controller, interconnects, ... and related design, integration and verification challenges

Preferred Qualifications

One or multiple qualifications in the list below would be a great advantage:

• SoC high speed protocols and chiplet architectures
• Coherency protocols
• Functional Safety / ASIL standards (ISO26262)
• Language proficiency (CEFR minimum grade): English (B2); French (B2)

Keywords

• SoC, ASIC, Deployment, Solutions Architect, Interconnect, Cache, CPU, GPU, Coherency, debug, power, functional safety

Minimum Qualifications:

OR

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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