{"id":4187892,"url":"https://alion.io/job/qualcomm-asic-validation-engineer-3","title":"ASIC Validation Engineer","company":{"id":4454000,"name":"Qualcomm","domain":"qualcomm.co.in","url":"https://alion.io/company/qualcomm-4","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"CI/CD","optional":true},{"name":"Confluence","optional":true},{"name":"Git","optional":true},{"name":"Jira","optional":true},{"name":"Linux","optional":true}],"status":"live","first_seen_at":"2026-11-12T18:35:10Z","employer_posted_date":null,"last_verified_at":"2026-11-12T18:35:10Z","board_verified":false,"closed_at":null,"days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"General Summary:\nStrong programming skills in C and C++ for resource-constrained systems.\n\nProficient in Python programming.\n\nExcellent knowledge in low-level firmware/bare-metal HW/IP driver writing.\n\nRoot-cause analysis of silicon failures and hardware debug and failure isolation.\n\nPerformance characterization and power and thermal validation.\n\nIn-depth understanding of the hardware is a must.\n\nShould have exposure to hardware initialization, validation diagnostics development, and firmware optimizations.\n\nGood knowledge of how to use embedded development tools such as JTAG and associated debug tools.\n\nWork experience on ARM Cortex platform/MIPS/RISC-V CPUs.\n\nWork experience with FPGA-based platforms is a plus.\n\nShould have good knowledge of system software stack, power management, high-speed peripherals, USB, SDIO, Ethernet, PCIe, etc. and memory subsystems like DDR/LPDDR, etc.\n\nExposure to PCIe Gen4/Gen5/Gen6, 25G/50G/100G/200G/400G Ethernet, CXL, DDR4/DDR5/LPDDR, SerDes, UCIe interface validation.\n\nFamiliarity with software configuration management tools, defect tracking tools, and peer review.\n\nWork experience on heterogeneous and multiprocessor SoC platforms.\n\nExposure to pre-silicon environment with RTL co-simulations is a plus point.\n\nExperience with development environments such as Linux, Git, Jira, and Confluence.\n\nStrong communication skills to exchange ideas and work as a team.\n\nResponsibilities:\nDevelop low-level drivers, bootloaders, BSPs, middleware, and application firmware.\nWork closely with hardware, RTL, and DV engineers to develop and debug.\nLead post-silicon bring-up and validation of a given module of ASIC/SoC products.\nDrive debug and root-cause analysis of silicon, firmware, and system-level issues.\nDevelop firmware and low-level software required for silicon bring-up, subsystem enablement, and debug.\nDebug complex hardware-software integration issues using oscilloscopes, logic analyzers, protocol analyzers, JTAG/SWD debuggers, and other laboratory equipment.\nAnalyze protocol traces, link training behavior, LTSSM states, error logs, and performance bottlenecks.\nDevelop production-quality software, including testing, documentation, static analysis, and CI/CD/CT.\nDevelop Python-based automation frameworks for validation and regression testing.\nInteract with hardware, software, and other teams to validate SoCs with minimum delays.\n\nMinimum Qualifications:\nBachelor's degree in Science, Engineering, or related field.\nSkills\nARM, ASIC, Baremetal, Debug, FPGA, Firmware, JTAG, SOC, Validation","description_format":"text","description_chars":2554,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-11-12T18:35:10Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring 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