{"id":47653,"url":"https://alion.io/job/qualcomm-cad-and-ppa-methodology-engineer","title":"CAD and PPA Methodology Engineer","company":{"id":94,"name":"Qualcomm","domain":"qualcomm.com","url":"https://alion.io/company/qualcomm","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":72,"open_postings":1182,"ghost_share":0.22,"stale_share":0.121,"repost_share":0.468,"time_to_fill_p50_days":75,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Diego, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":169500,"max":254300,"currency":"USD","period":"year","gross":null,"usd_annual":254300},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Rest-Assured","optional":true},{"name":"Synopsys Fusion Compiler","optional":true},{"name":"Synopsys PrimePower","optional":true},{"name":"Synopsys PrimeTime","optional":true},{"name":"Unix","optional":true}],"status":"live","first_seen_at":"2025-08-14T00:00:00Z","employer_posted_date":"2026-09-17","last_verified_at":"2026-10-17T20:46:45Z","board_verified":true,"closed_at":null,"days_open":429,"trust":{"level":"ghost","repost_count":2,"flags":["stale","repost"],"days_open":429},"description":"Company:\nQualcomm Technologies, Inc.Job Area:\nEngineering Group, Engineering Group > GPU ASICS Engineering General Summary:\nAs a member of the Graphics team, the successful applicant will help develop new flows/methodologies and algorithms to improve power, performance and area (PPA) on state-of-the-art GPU cores while working closely with the graphics microarchitecture design and implementation teams. The successful candidate will possess basic understanding of RTL design and ASIC design flow from RTL to GDS such as synthesis, static timing analysis, formal verification, physical design, ECO generation and verification. They will collaborate with multiple functional teams including design, technology, power, implementation, sign-off and post-silicon to drive PPA improvements into GPU cores.\nKnowledge and experience in the following is a definite advantage:\n· Implementation and delivery of GPU cores from RTL to GDSII\n· Semi-custom design flow and methodology development\n· Identifying areas for flow and process improvements\n· Verilog and System-Verilog languages\n· RTL synthesis using physically aware tools\n· Design constraint management for power, timing, clocking, interfaces\n· Formal Verification for RTL-netlist and netlist-netlist checks\n· Clock Tree Analysis and Optimization\n· ECO methods for functional and timing fixes\n· Managing design goals and tradeoffs in power, performance, and area\nPreferred Qualifications\nAt-least 5-7 years of experience developing methodologies for PPA improvement\nBasic understanding of digital design and RTL development\n Hands on experience with EDA tools such as Synopsys Fusion Compiler, Synopsys RTL-Architect, PrimePower,PrimeTime and Prime Closure\nScript writing experience in UNIX shell, Python, Perl and/or TCL\nExcellent interpersonal and analytical skills as well as ability to work independently\nHighly motivated, excellent team spirit, obsession with deliverable quality and customer oriented\nMinimum Qualifications:\n• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.OR\nMaster's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.\nOR\nPhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.\nQualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\nTo all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\nEEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\nPay rangeand Other Compensation & Benefits :\n$169,500.00 - $254,300.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.\nIf you would like more information about this role, please contact Qualcomm Careers.","description_format":"text","description_chars":5424,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","Car Electronics"],"lifecycle":[{"event":"open","at":"2025-08-14T00:00:00Z"},{"event":"close","at":"2026-08-09T14:49:34Z"},{"event":"reopen","at":"2026-09-11T12:35:39Z"},{"event":"close","at":"2026-09-11T16:54:35Z"},{"event":"reopen","at":"2026-09-12T16:53:34Z"},{"event":"close","at":"2026-09-12T19:53:34Z"},{"event":"reopen","at":"2026-09-14T09:46:52Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 55 · green card filings: 6","filings_12m":55,"filings_prev_12m":87,"green_card_filings_12m":6,"median_offered_wage_usd":122008,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":6,"band":"cold","label":"Long shot","p_open":1,"p_active":0.231,"p_room":0.28,"age_days":429,"expected_fill_days":75,"reasons":["conf:1","repost:2","velocity","ghost","win:tail","crowd:brand"],"computed_at":"2026-10-17T05:46:00Z"},"pay":{"stated_usd_annual":254300,"is_top_pay":true},"html_url":"https://alion.io/job/qualcomm-cad-and-ppa-methodology-engineer","json_url":"https://alion.io/job/qualcomm-cad-and-ppa-methodology-engineer.json","meta":{"generated_at":"2026-10-17T22:25:51Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":347,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-18T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":94},"rest":"https://alion.io/mcp/rest/get_company?id=94"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fqualcomm-cad-and-ppa-methodology-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fqualcomm-cad-and-ppa-methodology-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fqualcomm-cad-and-ppa-methodology-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/qualcomm-cad-and-ppa-methodology-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fqualcomm-cad-and-ppa-methodology-engineer"}]}