{"id":1672106,"url":"https://alion.io/job/qualcomm-ddr-phy-senior-lead-digital-design-engineer","title":"DDR PHY Senior Lead Digital Design Engineer","company":{"id":94,"name":"Qualcomm","domain":"qualcomm.com","url":"https://alion.io/company/qualcomm","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":71,"open_postings":1166,"ghost_share":0.225,"stale_share":0.125,"repost_share":0.466,"time_to_fill_p50_days":75,"computed_at":"2026-10-19T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":31000,"max_usd":70000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":696},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Rest-Assured","optional":true}],"status":"live","first_seen_at":"2026-09-25T00:00:00Z","employer_posted_date":"2026-09-30","last_verified_at":"2026-10-19T06:16:24Z","board_verified":true,"closed_at":null,"days_open":24,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":24},"description":"Company:\nQualcomm India Private LimitedJob Area:\nEngineering Group, Engineering Group > ASICS Engineering General Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\nMinimum Qualifications:\n• Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\nOR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\nRole Overview\nWe are seeking a motivated and technically strong DDR PHY Digital Design Engineer to join our team working on next-generation memory interface IPs. The candidate will be responsible for the architecture, RTL implementation, verification support, synthesis, low-power design, DFT, and silicon bring-up of high-performance DDR PHY solutions used in leading-edge SoC products.\nResponsibilities\nDesign and develop digital components of high-performance DDR PHY for LPDDR/DDR memory interfaces.\nParticipate in micro-architecture definition, RTL coding, integration, and debug of complex digital IPs.\nDrive RTL quality and signoff through lint, clock-domain crossing (CDC), reset-domain crossing (RDC), low-power, and design rule checks.\nCollaborate with the functional verification team to develop verification plans, review coverage closure, and debug design issues.\nDevelop synthesis and timing constraints, analyze timing reports, and deliver high-quality netlists for physical design implementation.\nCreate and maintain UPF-based low-power intent and perform equivalence checking, and low-power signoff.\nImplement and validate Design-for-Test (DFT) features, support scan insertion, ATPG generation, and optimize stuck-at and transition fault coverage.\nWork closely with physical design, STA, DFT, verification, and SoC integration teams to achieve project milestones and quality targets.\nSupport pre-silicon and post-silicon bring-up, characterization, debug, and issue resolution across multiple product programs.\nContribute to methodology improvements, automation, and design flow enhancements to improve engineering productivity and quality.\nRequired Qualifications\nB.Tech/M.Tech in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.\n5+ years of experience in digital design and front-end implementation of complex ASIC/SoC/IP designs.\nStrong understanding of digital design fundamentals, RTL development using Verilog/SystemVerilog, and micro-architecture concepts.\nHands-on experience with front-end design flows, including:Lint\nCDC/RDC\nLow-power verification\nSynthesis\nStatic Timing Analysis (STA)\nDesign-for-Test (DFT)\n\nFamiliarity with industry-standard EDA tools used for RTL design, verification, synthesis, and timing closure.\nStrong debugging and problem-solving skills.\nExcellent teamwork, communication, and collaboration skills with global engineering teams.\nPreferred Qualifications\nExperience in DDR/LPDDR PHY, high-speed interface, or mixed-signal IP development.\nKnowledge of UPF, power-aware design methodologies, and low-power architecture techniques.\nFamiliarity with scan insertion, ATPG, and silicon debug activities.\nExposure to post-silicon bring-up, validation, and characterization.\nExperience working across multi-functional teams, including verification, physical design, DFT, firmware, and system engineering.\nWhat You'll Work On\nLPDDR5/LPDDR6 and future-generation memory PHY solutions.\nHigh-performance, low-power digital architectures for mobile, compute, XR, automotive, and AI platforms.\nState-of-the-art design methodologies spanning RTL design through silicon validation.\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\nTo all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\nIf you would like more information about this role, please contact Qualcomm Careers.","description_format":"text","description_chars":6143,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Autonomous Driving","Energy Efficiency","Car Electronics"],"lifecycle":[{"event":"open","at":"2026-10-02T07:04:59Z"}],"visa":[],"liveness":{"score":85,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.845,"p_room":1,"age_days":24,"expected_fill_days":75,"reasons":["conf:3","velocity","win:early","comp:brand"],"computed_at":"2026-10-19T05:45:15Z"},"pay":null,"html_url":"https://alion.io/job/qualcomm-ddr-phy-senior-lead-digital-design-engineer","json_url":"https://alion.io/job/qualcomm-ddr-phy-senior-lead-digital-design-engineer.json","meta":{"generated_at":"2026-10-19T08:46:36Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":6057,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-20T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":94},"rest":"https://alion.io/mcp/rest/get_company?id=94"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fqualcomm-ddr-phy-senior-lead-digital-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fqualcomm-ddr-phy-senior-lead-digital-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fqualcomm-ddr-phy-senior-lead-digital-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/qualcomm-ddr-phy-senior-lead-digital-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fqualcomm-ddr-phy-senior-lead-digital-design-engineer"}]}