DV Power Vectors & Window Extraction Engineer (Staff/Sr Staff)

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General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/opticalsystems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

We are looking for a talented engineer to join our team and drive power-vector development, execution, analysis, and window extraction across simulation, emulation, and silicon-validation environments.

This role is ideal for someone passionate about Design Verification, low-power design, power analysis, waveform debugging, and cross-functional execution.

Key Responsibilities:

[1]. Develop and execute DV power vectors covering key workloads, power states, transitions, boot flows, retention, reset, and stress scenarios.

[2]. Bring up and maintain simulation, emulation, and power-aware verification environments.

[3]. Analyze waveforms, activity dumps, power reports, and execution logs to identify meaningful power-analysis windows.

[4]. Extract and document windows for peak power, average power, dynamic voltage drop, thermal analysis, and pre-silicon/post-silicon correlation.

[5]. Debug vector failures, power-state sequencing issues, missing activity, waveform mismatches, and unexpected power behavior.

[6]. Collaborate closely with DV, Design, Power, Physical Design, Emulation, PTE, and Post-Silicon teams.

[7]. Maintain traceability between test cases, configurations, waveforms, extracted windows, and delivered vector collateral.

Requirements :

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• 7-15 years of experience in Design Verification, power-aware verification, vector development, or power analysis.
• Strong understanding of: RTL simulation and waveform analysisSystemVerilog/UVM or equivalent verification environmentsLow-power concepts, power states, clock gating, retention, and isolationSimulation, emulation, GLS, or silicon-validation flowsPower estimation and activity analysis
• Proficiency with scripting languages such as Python, Perl, Shell, or Tcl.
• Experience using waveform-debug and power-analysis tools.
• Ability to identify representative, peak, and corner-case power windows.
• Strong debugging, analytical, documentation, and communication skills.
• Experience working across multiple engineering teams in a fast-paced environment.

Good to Have :

• Experience with UPF and power-intent verification.
• Knowledge of CPU, SoC, memory, interconnect, or subsystem power behavior.
• Experience with dynamic voltage drop, IR-drop, VMIN, or thermal analysis.
• Familiarity with emulation platforms and large-scale workload execution.
• Experience correlating pre-silicon power results with post-silicon measurements.
• Understanding of frequency-voltage operating points and power-performance tradeoffs.

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