{"id":837645,"url":"https://alion.io/job/qualcomm-firmware-engineer-serdes-phy-all-levels","title":"Firmware Engineer – SerDes PHY (all levels)","company":{"id":94,"name":"Qualcomm","domain":"qualcomm.com","url":"https://alion.io/company/qualcomm","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":71,"open_postings":1166,"ghost_share":0.225,"stale_share":0.125,"repost_share":0.466,"time_to_fill_p50_days":75,"computed_at":"2026-10-19T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Toronto, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":83000,"max_usd":145000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":57},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Embedded C","optional":false},{"name":"Java","optional":false},{"name":"JTAG Debuggers","optional":false},{"name":"Linux","optional":false},{"name":"MATLAB","optional":false},{"name":"Python","optional":false},{"name":"RTOS","optional":false},{"name":"Verilog","optional":false},{"name":"Agile","optional":true},{"name":"Bash","optional":true},{"name":"C","optional":true},{"name":"Confluence","optional":true},{"name":"Jira","optional":true},{"name":"Rest-Assured","optional":true},{"name":"Scrum","optional":true},{"name":"SystemVerilog","optional":true}],"status":"live","first_seen_at":"2026-09-03T00:00:00Z","employer_posted_date":"2026-09-17","last_verified_at":"2026-10-19T10:38:12Z","board_verified":true,"closed_at":null,"days_open":46,"trust":{"level":"ok","repost_count":2,"flags":["repost"],"days_open":46},"description":"Company:\nQualcomm Canada ULCJob Area:\nEngineering Group, Engineering Group > Software EngineeringGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world class products that meet and exceed customer needs. Qualcomm Software Engineers collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain information on performance requirements and interfaces.Replacement Position\nMinimum Qualifications:\n• Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Engineering or related work experience.OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Software Engineering or related work experience.\nOR\nPhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience.\n• 3+ years of work experience with Programming Language such as C, C++, Java, Python, etc.\nWe’re building the world’s most advanced SerDes PHY for use in AI data centers and beyond.The Embedded Software /Firmware Team atQualcomm develops critical embedded software that powers high-performance multi-standard Serializer/Deserializer(SerDes) PHY IP used in next-generation data center, AI/ML, automotive, and compute applications. Our SerDes IPs support standards such as PCIe, Ethernet, CXL,andare integrated into SoCs,ASICs, and chipletsbuilt by leading semiconductor companies around the world.\nThe firmware team owns the full embedded software stack that controls the SerDes hardware, including low-level embedded firmware, customer-facing C SDKs,demo &automation scripts, and interactive tools. As a key enabler of silicon bring-up, validation, and production deployment, we work closely with hardware, systems, DV,validation,and application teams across the product lifecycle-from early development to high-volume manufacturing.\nWe are looking for an experienced Firmware Engineer to lead firmware architecture, development, integration, and bring-up for our SerDes PHY portfolio. The ideal candidate has driven firmware definition, architecture, and development starting from the RTL/digital design phase with EDA tool/simulator integration, all the way through to the post-silicon phase with device-level bring-up and debug. This is a highly collaborative role: you will work with hardware, systems, and software teams to drive requirements and successful chip bring-up; with firmware and embedded software engineers to drive code re-use across the organization; and with program managers to identify and meet deadlines. This individual will be instrumental in building next-generationSERDES PHYIP and semiconductors that meet Qualcomm’s high performance and quality standards.\nWhat You Can Expect\nCore responsibilities for the firmware team include:\nEmbedded firmware running on RISC-V-based controllers that manage Qualcomm’s advanced SerDesdatapaths\n\nPython and C SDKs provided to internal SoC teams and external customers for SerDes bring-up, calibration, tuning, and diagnostics\n\nPython-based lab tools and GUIs for interactive debug, register access, and validation\n\nBuild, regression, and CI infrastructure to ensure code quality and full coverage.\n\nYou’ll play a key leadership role in delivering robust, production-quality firmware for SerDes PHY IP. You’ll help define architecture, drive features end-to-end, coordinate across cross-functional teams, and directly influence the design and usability ofQualcomm’sdesigns.\nIn this position, you will be:\nTechnical or project lead for SerDes firmware on a major IP program, working with a team (2-8 engineers) through planning, development, validation, and customer delivery\n\nOwning the entire firmware lifecycle for SerDes PHY, from pre-silicon design through post-silicon validation and optimization\n\nGathering requirements, studying high-level designs, developing device interface functions, and turning small building blocks into higher-level firmware system design\n\nArchitecting and implementing embedded C/C++ firmware for hardware calibration, training algorithms, DSP adaptations, and link state management\n\nWorking with multi-functional teams - ASIC/digital design, digital verification, software, and systems engineering - to define detailed bring-up and validation requirements and meet performance goals\n\nCommunicating requirements and coordinating execution across multiple teams and sites\n\nTranslating bring-up and validation requirements into efficient C/C++ firmware code and well-structured software organization\n\nTranslating protocol specifications (e.g. PCIe, Ethernet, CXL, UCIe) or custom system-level requirements into internal firmware architecture and documentation\n\nDeveloping test and debug capabilities that help guide hardware design decisions for future product iterations\n\nDebugging complex lab and field issues in conjunction with hardware, applications, and validation teams, and driving low-level SW, silicon, and HW issues to root cause and closure\n\nDriving multi-functional teams and partners to address integration and bring-up challenges, ensuring chips are seamlessly brought up, validated, tested, and meet product and business requirements\n\nPlanning and developing test cases that improve reliability and release quality for internal and external stakeholders, and ensuring they run continuously in regression\n\nWorking with external vendors and customers to ensure requirements are met and releases are of high quality\n\nDriving and collaborating across functions to define FW milestones, plan sprints, close tickets, and deliver reliable, high-quality features\n\nImplementing industry best practices and documenting firmware and hardware design specifications and decisions\n\nMentoring junior engineers, promoting team building, and driving continuous improvement in processes and techniques\n\nDemonstrating full ownership of assigned systems/components, managing timelines and resolving project challenges to meet program timing\n\nStaying current with advancements in the semiconductor industry and incorporating relevant innovations into our processes\n\nSupporting development and silicon bring-up across Qualcomm teams and other sites\n\nExampleProblems You’ll Solve\nMentoring a junior engineer through a hard-to-reproduce PHY calibration bug seen in customer silicon\n\nDeveloping architecture and state machines to handle multi-lane synchronization or adaptive equalization across dynamic conditions\n\nPorting a high-level MATLAB or Python SerDes calibration algorithm to optimized fixed-point firmware\n\nCreating a SerDes diagnostics framework accessible via both SDK and GUI\n\nUsing simulation environments, EDA tool integration, and FPGA emulation to validate FW behavior beforetapeout\n\nBuilding error monitoring and board/interface configuration APIs that make link health observable to SoC software teams\n\nStanding up a regression suite that catches link-training regressions before a customer release ships\n\nWorking with IP hardware architects to influence future revisions based on field debug learnings\n\nWhat We’re Looking For\nBS/MS in Computer Science, Electrical Engineering, Computer Engineering, or a related field\n\n7+ years of experience in embedded C/C++ firmware development for hardware IP or SoCs, with strong proficiency in C/C++ and Python\n\nHands-on experience with embedded architectures such as ARM, RISC-V, or MIPS, and with low-level programming on bare metal, RTOS, BIOS/UEFI firmware, Linux kernel, or device drivers\n\nTechnical or team leadership experience in embedded software projects from spec to production\n\nDeep understanding of microcontroller architecture (RISC-V a plus), memory-mapped registers, ISRs, and boot flows\n\nSystems mindset and experience developing SW/FW to control analog, digital, and mixed-signal circuits\n\nExperience with SerDes, Ethernet, PCIe, CXL, or D2D/UCIe/chiplet products and communication systems\n\nStrong lab debug skills, working directly on silicon with scopes, JTAG debuggers, I2C/SPI tools, analyzers, and custom tooling, including bring-up and diagnostics of high-speed signals\n\nFamiliarity with industry-standard EDA tools and methodologies used for digital verification, and with HDLs such as Verilog andSystemVerilog\n\nFamiliarity with git and modern software development methodologies\n\nExcellent organizational and communication skills, a willingness to learn, and the ability to collaborate across functions and geographies\n\nPreferred Experience:\nKnowledge of SerDes and high-speed IO standards (PCIe, Ethernet, UCIe, CXL, etc.)\n\nExperience with calibration algorithms, signal conditioning, and adaptive feedback control in hardware\n\nExperience in silicon bring-up and post-silicon debug\n\nExperience in pre-silicon firmware development (DV, emulation, etc.)\n\nKnowledge of RTOS or bare-metal FW architectures, including embedded Linux development,Buildroot/Yocto, andRTOSessuch as Zephyr andFreeRTOS\n\nKnowledge of peripherals and protocols such as 1G/10G Ethernet, DDR, I2C, SPI/QSPI, MIPI/CSI, GMSL, A2B, I2S, TDM, LVDS, PCIe, USB,NVMe, and CAN\n\nExperience developing drivers for multiple devices at the PCB level to interact with whole systems\n\nExperience creating error monitoring and board/interface configuration APIs\n\nHands-on lab validation experience with CPU, SoC, FPGA, MCU, and DSP components, including developing tests and debug tools\n\nExperience working with FPGAs such as Xilinx, Zed, and MicroZed\n\nHardware hands-on and debugging experience, such as power, SI, and EMC validation and tuning\n\nScripting in Python, Bash, etc. for lab automation and testing\n\nFamiliarity with digital design concepts (Verilog/SystemVerilog), simulation, and DV flows\n\nExposure to the OSI model, especially the physical and data link layers\n\nUnderstanding of signal processing concepts such as eye diagrams, jitter, BER, SNR, and CTLE/DFE/FFE\n\nExperience with Jira, Agile/Scrum, and Confluence\n\nContributions toopen sourceprojects\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\nTo all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. 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