GPU STA/Timing Engineer (Senior Lead/Staff)

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General Summary:

Job Overview

Qualcomm's GPU team is looking for experienced STA Engineers to drive timing signoff and closure for next-generation high-performance GPU designs. The role involves close collaboration with Architecture, RTL, Physical Design, DFT, and SoC teams to deliver best-in-class silicon products.

Responsibilities

• Own block-level and full-chip STA signoff for GPU designs.

• Develop and validate timing constraints (SDC).

• Perform MCMM/MMMC timing analysis, timing closure, and ECO implementation.

• Drive setup/hold, noise, SI, and low-power timing closure.

• Collaborate with cross-functional teams to resolve timing issues.

• Enhance STA methodologies, signoff flows, and automation.

• Mentor junior engineers and provide technical leadership.

Required Qualifications

• BS/MS in Electrical/Electronics Engineering or related field.

• 6-10 years of experience in ASIC/SoC STA and timing signoff.

• Strong expertise in STA, MCMM/MMMC, SDC, timing closure, ECOs, SOCV/AOCV, and SI analysis.

• Hands-on experience with Synopsys PrimeTime.

• Strong understanding of Physical Design concepts and implementation flows.

• Proficiency in Tcl/Python scripting.

Preferred Skills

• Experience with GPU, CPU, AI/ML, or high-performance SoC designs.

• Experience in advanced technology nodes (5nm and below).

• Exposure to Fusion Compiler, ICC2, StarRC, Tempus, or Innovus.

• Proven technical leadership and mentoring experience.

Minimum Qualifications:

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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