{"id":669008,"url":"https://alion.io/job/qualcomm-hardware-system-design-engineer-senior-or-staff","title":"Hardware System Design Engineer, Senior or Staff","company":{"id":94,"name":"Qualcomm","domain":"qualcomm.com","url":"https://alion.io/company/qualcomm","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"C","score":69,"open_postings":1038,"ghost_share":0.257,"stale_share":0.157,"repost_share":0.458,"time_to_fill_p50_days":74,"computed_at":"2026-11-04T06:34:25Z"}},"role":"DevOps","role_family":"DevOps","seniority":"staff","employment_type":null,"work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Diego, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":121800,"max":182600,"currency":"USD","period":"year","gross":null,"usd_annual":182600},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Ansys HFSS","optional":false},{"name":"Cadence Sigrity","optional":false},{"name":"HyperLynx","optional":false},{"name":"Linux","optional":false},{"name":"Microsoft Office","optional":false},{"name":"Unix","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Rest-Assured","optional":true}],"status":"live","first_seen_at":"2026-08-26T00:00:00Z","employer_posted_date":"2026-09-17","last_verified_at":"2026-11-04T11:21:57Z","board_verified":true,"closed_at":null,"days_open":70,"trust":{"level":"ok","repost_count":2,"flags":["repost"],"days_open":70},"description":"Company:\nQualcomm Technologies, Inc.Job Area:\nEngineering Group, Engineering Group > ASICS EngineeringGeneral Summary:\nHardware System Design Engineer, Senior Staff\nLocation: San Diego, CA (100% On-Site)Employment Type: Full-Time\nLevel: Senior or Staff - final level and title will be determined based on the selected candidate’s experience and demonstrated scope of impact.\nPosition Summary\nYou will be part of a hardware design team that builds high-performance FPGA-based emulation platforms. You will own the board design process - schematic capture, PCB stack-up, PCB layout, power and signal integrity simulation, BOM management, and design verification testing - while driving system-level architecture in close partnership with customers and software/firmware teams. You will work cross-functionally to evaluate design trade-offs, direct lab technicians through system installation and debug, and partner with design, CAD, and manufacturing teams on prototyping, testing, and production support. Candidates with broader scope and a track record of technical leadership may be considered at the Staff level, where they will additionally define system architecture across multiple boards/platforms, set design methodology and standards for the team, serve as the primary technical interface with customers, and mentor senior and junior engineers.\nKey Responsibilities\nOwn the board design lifecycle: schematic capture, PCB stack-up (26+ layers), PCB layout, BOM management, and design verification testing.\nDrive system-level architecture in collaboration with customers, software, and firmware development teams.\nPerform power and signal integrity simulations for 10 Gbps+ SERDES and high-speed I/O, from model extraction through simulation, reporting, and recommended design changes.\nLead or support FPGA board design (Xilinx and/or Altera), including DDR3/DDR4/DDR5 discrete memory subsystems.\nDirect lab technicians on system installation, bring-up, and debug of boards and multi-board systems, including root-cause investigation of the most complex issues.\nCollaborate with mechanical, PCB layout, and manufacturing teams to ensure designs are optimized for signal integrity, manufacturability (DFM), and reliability.\nAuthor and maintain design documentation (HDDs, pinout tables, design review packages) to support cross-team alignment and program reviews.\nServe as a key or primary technical point of contact with customers and cross-functional stakeholders on system architecture decisions and trade-offs.\nSupport factory/production builds and new product introduction (NPI) activities as needed.\nRequired Qualifications & Experience\nCore Board Design & Signal Integrity\nExperience with the board design process including schematic capture, PCB stack-up, PCB layout (26+ layers), BOM management, and design verification testing.\nExperience with FPGA board design (Xilinx and/or Altera).\nFPGA HDL coding experience.\nExperience with 10 Gbps or higher SERDES board designs.\nExperience performing power and signal integrity simulations for 10 Gbps+ signals, including various I/O analyses, using established methodologies from model extraction through simulation, reporting, and recommending design changes to address failing simulations.\nExperience with circuit and layout guidelines, high-speed design concepts, signal integrity, and transmission line theory.\nExperience with DDR3/DDR4/DDR5 discrete component board designs.\nSystem architecture design experience; candidates for the Staff level should have experience defining architecture across multiple boards/platforms.\nProtocols, Tools & Test Equipment\nFamiliarity with I2C, JTAG, UART, SPI, SD Card, PCIe, and eMMC protocols.\nFamiliarity with test equipment including oscilloscopes, logic analyzers, and protocol analyzers.\nBoard- and system-level bring-up and debug experience.\nBasic Linux/Unix experience.\nFamiliarity with Microsoft Office, Mentor Graphics DxDesigner/Expedition, Vivado, Quartus, HyperLynx, Sigrity PowerSI/PowerDC, ADS, Ansys HFSS, and SPICE.\nCollaboration & Professional Skills\nProven ability to work with cross-functional teams (mechanical, PCB layout, manufacturing, software/firmware, program management) to deliver high-quality boards and systems on schedule.\nStrong written and verbal communication skills, including the ability to present design trade-offs and simulation results to technical, customer, and cross-functional audiences.\nDemonstrated ability to work independently, prioritize competing priorities, and drive tasks to closure with minimal supervision.\nExperience mentoring or providing technical guidance to junior engineers; Staff-level candidates should also demonstrate experience mentoring senior engineers and leading design reviews.\nPreferred Qualifications (Nice to Have)\nPower supply design experience.\nExperience with signal integrity and PDN (power delivery network) simulations.\nExperience with Design for Manufacturing (DFM) and Design for Test (DFT) reviews with PCB fabricators and contract manufacturers.\nFamiliarity with scripting languages (Python, Perl) for design automation, data extraction, or test/analysis workflows.\nIndustry certification such as IPC Certified Interconnect Designer (CID) or equivalent.\nExperience supporting a product from concept through production release and factory NPI.\n(Staff) Experience defining board/system design methodology or reusable IP/standards adopted across multiple programs, and/or prior experience as a technical lead or architect on a hardware program.\nEducation & Experience\n5+ years’ experience in system architecture, hardware board design, and signal integrity simulations required; 10+ years typically expected for consideration at the Staff level.\nBachelor’s or Master’s Degree in Electrical/Electronics Engineering, Computer Engineering, or a related field - or equivalent practical experience.\nAdditional Requirements\nThis is a 100% on-site position based in San Diego, CA; the role requires regular in-person lab access to support system installation, bring-up, and debug, and is not eligible for remote or hybrid work.\nAbility to lift/move lab equipment and boards as needed, and to work in a lab environment for extended periods during bring-up and debug cycles.\nMinimum Qualifications:\n• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\nOR\nPhD in Science, Engineering, or related field.\nQualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\nTo all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\nEEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\nPay rangeand Other Compensation & Benefits :\n$121,800.00 - $182,600.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.\nIf you would like more information about this role, please contact Qualcomm Careers.","description_format":"text","description_chars":9451,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","Car Electronics"],"lifecycle":[{"event":"open","at":"2026-09-10T22:14:10Z"},{"event":"close","at":"2026-09-11T02:22:19Z"},{"event":"reopen","at":"2026-09-12T16:53:34Z"},{"event":"close","at":"2026-09-12T19:53:34Z"},{"event":"reopen","at":"2026-09-12T22:53:34Z"},{"event":"close","at":"2026-09-13T01:53:42Z"},{"event":"reopen","at":"2026-09-13T05:40:27Z"},{"event":"close","at":"2026-09-13T08:50:22Z"},{"event":"reopen","at":"2026-09-13T17:50:41Z"},{"event":"close","at":"2026-09-13T23:50:53Z"},{"event":"reopen","at":"2026-09-15T06:57:51Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 55 · green card filings: 6","filings_12m":55,"filings_prev_12m":87,"green_card_filings_12m":6,"median_offered_wage_usd":122008,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":18}],"liveness":{"score":38,"band":"fade","label":"Fading","p_open":1,"p_active":0.64,"p_room":0.6,"age_days":70,"expected_fill_days":74,"reasons":["conf:4","repost:2","velocity","win:late","crowd:brand"],"computed_at":"2026-11-04T06:34:25Z"},"pay":{"stated_usd_annual":182600,"is_top_pay":false},"html_url":"https://alion.io/job/qualcomm-hardware-system-design-engineer-senior-or-staff","json_url":"https://alion.io/job/qualcomm-hardware-system-design-engineer-senior-or-staff.json","meta":{"generated_at":"2026-11-04T15:17:53Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":23267,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-05T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":94},"rest":"https://alion.io/mcp/rest/get_company?id=94"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fqualcomm-hardware-system-design-engineer-senior-or-staff"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fqualcomm-hardware-system-design-engineer-senior-or-staff"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fqualcomm-hardware-system-design-engineer-senior-or-staff"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/qualcomm-hardware-system-design-engineer-senior-or-staff\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fqualcomm-hardware-system-design-engineer-senior-or-staff"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":669008}},{"tool":"search_jobs","arguments":{"company":"qualcomm.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":669008},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); 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