NPU Synthesis Engineer, Principal

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General Summary:

Job Overview

We are seeking a highly motivated Synthesis Engineer/Lead to join our NPU (Neural Processing Unit) design team. In this role, you will drive RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators used in next-generation SoCs. You will work closely with Architecture, RTL Design, STA, DFT, and Physical Design teams to deliver high-quality, power-efficient silicon on advanced technology nodes.

Minimum Qualifications:

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Key Responsibilities

• Own RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.
• Develop and maintain synthesis flows, constraints, and automation for complex hierarchical designs.
• Drive pre-layout and post-layout timing closure across multiple modes and process corners.
• Optimize designs for PPA (Performance, Power, Area) targets using physical-aware synthesis methodologies.
• Create, validate, and maintain timing constraints (SDC), clock definitions, false paths, and multi-cycle paths.
• Collaborate with RTL, DFT, STA, and Physical Design teams to resolve QoR, timing, power, and convergence issues.
• Perform quality checks including LEC, CDC, lint, and low-power verification.
• Analyze and improve synthesis QoR through scripting and flow enhancements.
• Support tapeout activities and drive continuous improvements in synthesis methodologies.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.
• Strong understanding of ASIC design flow from RTL to GDS.
• Hands-on experience with RTL synthesis, timing closure, and constraint development.
• Expertise in Synopsys Design Compiler/Fusion Compiler or Cadence Genus.
• Strong timing analysis knowledge using PrimeTime.
• Experience with low-power design methodologies and UPF-based flows.
• Good understanding of clocking architecture, timing constraints, and timing signoff.
• Proficiency in TCL and scripting languages such as Python or Perl.
• Excellent debugging, problem-solving, and cross-functional collaboration skills.

Preferred Qualifications

• Experience working on AI/ML accelerators, NPU, DSP, GPU, CPU, or other high-performance compute architectures.
• Knowledge of advanced technology nodes (5nm, 4nm, 3nm and below).
• Experience with physical-aware synthesis and hierarchical design methodologies.
• Familiarity with LEC, CDC, lint, power analysis, and low-power verification flows.
• Proven track record of successful SoC or IP tapeouts.

Experience

• Senior Engineer: 3-5 years of relevant experience.
• Lead Engineer: 5-8 years of relevant experience.
• Staff Engineer: 8-12 years of relevant experience.
• Sr Staff Engineer: 12-18 years of relevant experience.
• Principal Engineer: 18+ years of relevant experience.

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