{"id":1723477,"url":"https://alion.io/job/qualcomm-npu-aiprocessor-synthesis-engineer-sr-lead","title":"NPU AI/Processor Synthesis Engineer- Sr Lead","company":{"id":94,"name":"Qualcomm","domain":"qualcomm.com","url":"https://alion.io/company/qualcomm","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":72,"open_postings":1175,"ghost_share":0.222,"stale_share":0.123,"repost_share":0.468,"time_to_fill_p50_days":74,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India","Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":31000,"max_usd":71000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Genus","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Rest-Assured","optional":true}],"status":"live","first_seen_at":"2026-08-21T00:00:00Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-21T17:31:42Z","board_verified":true,"closed_at":null,"days_open":61,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":61},"description":"Company:\nQualcomm India Private LimitedJob Area:\nEngineering Group, Engineering Group > Hardware Engineering General Summary:\nJob Overview\nWe are seeking a highly motivated Synthesis Engineer/Lead to join our NPU (Neural Processing Unit) design team. In this role, you will drive RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators used in next-generation SoCs. You will work closely with Architecture, RTL Design, STA, DFT, and Physical Design teams to deliver high-quality, power-efficient silicon on advanced technology nodes.\nMinimum Qualifications:\n• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\nOR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\nKey Responsibilities\nOwn RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.\nDevelop and maintain synthesis flows, constraints, and automation for complex hierarchical designs.\nDrive pre-layout and post-layout timing closure across multiple modes and process corners.\nOptimize designs for PPA (Performance, Power, Area) targets using physical-aware synthesis methodologies.\nCreate, validate, and maintain timing constraints (SDC), clock definitions, false paths, and multi-cycle paths.\nCollaborate with RTL, DFT, STA, and Physical Design teams to resolve QoR, timing, power, and convergence issues.\nPerform quality checks including LEC, CDC, lint, and low-power verification.\nAnalyze and improve synthesis QoR through scripting and flow enhancements.\nSupport tapeout activities and drive continuous improvements in synthesis methodologies.\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.\nStrong understanding of ASIC design flow from RTL to GDS.\nHands-on experience with RTL synthesis, timing closure, and constraint development.\nExpertise in Synopsys Design Compiler/Fusion Compiler or Cadence Genus.\nStrong timing analysis knowledge using PrimeTime.\nExperience with low-power design methodologies and UPF-based flows.\nGood understanding of clocking architecture, timing constraints, and timing signoff.\nProficiency in TCL and scripting languages such as Python or Perl.\nExcellent debugging, problem-solving, and cross-functional collaboration skills.\nPreferred Qualifications\nExperience working on AI/ML accelerators, NPU, DSP, GPU, CPU, or other high-performance compute architectures.\nKnowledge of advanced technology nodes (5nm, 4nm, 3nm and below).\nExperience with physical-aware synthesis and hierarchical design methodologies.\nFamiliarity with LEC, CDC, lint, power analysis, and low-power verification flows.\nProven track record of successful SoC or IP tapeouts.\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\nTo all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\nIf you would like more information about this role, please contact Qualcomm Careers.","description_format":"text","description_chars":4849,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Autonomous Driving","Energy Efficiency","Car Electronics"],"lifecycle":[{"event":"open","at":"2026-10-02T21:23:27Z"}],"visa":[],"liveness":{"score":60,"band":"ok","label":"Likely open","p_open":1,"p_active":0.803,"p_room":0.75,"age_days":61,"expected_fill_days":74,"reasons":["conf:2","velocity","win:late","comp:brand"],"computed_at":"2026-10-21T05:46:15Z"},"pay":null,"html_url":"https://alion.io/job/qualcomm-npu-aiprocessor-synthesis-engineer-sr-lead","json_url":"https://alion.io/job/qualcomm-npu-aiprocessor-synthesis-engineer-sr-lead.json","meta":{"generated_at":"2026-10-21T21:46:52Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":31013,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-22T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":94},"rest":"https://alion.io/mcp/rest/get_company?id=94"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fqualcomm-npu-aiprocessor-synthesis-engineer-sr-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fqualcomm-npu-aiprocessor-synthesis-engineer-sr-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fqualcomm-npu-aiprocessor-synthesis-engineer-sr-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/qualcomm-npu-aiprocessor-synthesis-engineer-sr-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fqualcomm-npu-aiprocessor-synthesis-engineer-sr-lead"}]}