{"id":698137,"url":"https://alion.io/job/qualcomm-physical-design-engineer-sr-staff-hod-hasharon","title":"Physical Design Engineer, Senior Staff - Hod Hasharon","company":{"id":94,"name":"Qualcomm","domain":"qualcomm.com","url":"https://alion.io/company/qualcomm","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"C","score":69,"open_postings":1046,"ghost_share":0.25,"stale_share":0.149,"repost_share":0.458,"time_to_fill_p50_days":74,"computed_at":"2026-11-02T06:13:15Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Haifa, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":115000,"max_usd":269000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1702},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"Ansys RedHawk","optional":false},{"name":"Cadence Innovus","optional":false},{"name":"Cadence Quantus","optional":false},{"name":"LLM","optional":false},{"name":"Python","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys StarRC","optional":false},{"name":"TCL Scripting","optional":false},{"name":"Rest-Assured","optional":true}],"status":"live","first_seen_at":"2026-06-03T00:00:00Z","employer_posted_date":"2026-10-01","last_verified_at":"2026-11-03T01:40:25Z","board_verified":true,"closed_at":null,"days_open":153,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":152},"description":"Company:\nQualcomm Israel Ltd.Job Area:\nEngineering Group, Engineering Group > ASICS Engineering General Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\nMinimum Qualifications:\n• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.OR\nMaster's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.\nOR\nPhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.\nWe are seeking a seasoned Sr Staff Physical Design Engineer to provide technical leadership across full-chip and multi-die physical implementation on advanced TSMC FinFET nodes. You will define and own the backend design methodology, champion Agentic AI integration into the PD flow, and mentor engineers across the team while interfacing directly with foundry, EDA vendors, and executive stakeholders.\nTSMC N5 / N4P / N3\nPython\nTCL\nAgentic AI\nFull-Chip PD\nFlow Architecture\nWhat You'll Do\nArchitect and own the full-chip physical design strategy: floorplanning, power delivery network (PDN), clock architecture, PnR, and timing closure\nDefine and drive backend methodology standards across the team for advanced node tapeouts (N5/N4P/N3)\nLead critical timing closure efforts - MCMM, OCV, advanced ECO strategies, and cross-corner sign-off\nOversee and guide signal integrity, power integrity, EM/IR, and reliability analysis for full-chip designs\nArchitect and lead the development of scalable PD flow infrastructure using Python and TCL - including automated regression, sign-off reporting, and run management systems\nChampion the adoption of Agentic AI in the design flow - define use cases, evaluate tools, prototype autonomous agents for floorplan exploration, timing closure, and ECO automation\nLead cross-functional design reviews with DFT, verification, analog, and process engineering teams\nInterface with TSMC, EDA vendors (Synopsys, Cadence, Siemens), and internal research teams to evaluate and adopt new methodologies\nMentor and technically guide junior and mid-level PD engineers across the organization\nWhat You'll Need\n10+ years of experience in digital Physical Design with a proven track record of tapeouts on FinFET nodes (N7 and below)\nDeep expertise in full-chip and block-level floorplanning, clock architecture, STA, PnR, and physical sign-off\nExpert proficiency in EDA tools: Synopsys ICC2/Fusion, Cadence Innovus, Calibre, PrimeTime, RedHawk / Voltus, StarRC / Quantus\nAdvanced Python and TCL scripting - ability to architect large-scale PD automation frameworks and flow infrastructure\nProven experience in flow development: designing, implementing, and owning end-to-end backend design flows at team or organization level\nDemonstrated experience or vision for applying Agentic AI methodologies to EDA challenges - autonomous agents, AI-driven optimization, LLM-assisted debugging\nStrong communication skills - ability to present methodology decisions, risk assessments, and tapeout readiness to senior management\nExperience with power optimization (DVFS, multi-Vt, power domains, UPF/CPF)\nPreferred Experience\nExperience with chiplets, 2.5D/3D IC physical design, or advanced packaging technologies\nFamiliarity with AI/ML-driven EDA tool evaluation and vendor collaboration\nPrior experience in a tech lead or staff engineering leadership role\n*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.\nQualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\nTo all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. 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