Physical Design Engineer- Staff to Sr. Staff

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General Summary:

QCT’s NSP Physical Design Team is actively seeking a highly experienced Clock Physical Design Engineer to develop, optimize, and sign off advanced clocking solutions for next-generation NSP designs. The ideal candidate will have 10+ years of ASIC/SoC physical design experience, with deep expertise in high-performance clock architecture and implementation, including clock H-trees, clock mesh, and clock spine methodologies.

This role requires strong understanding of the complete clock path, from clock source and distribution architecture through block-level implementation and signoff. The engineer will work across physical design, timing, power, PLL, and CAD teams to optimize clock performance, power, variation, noise, and robustness across advanced technology nodes.

Minimum Qualifications:

OR

Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Key Responsibilities

• Own and drive clock physical design methodology, implementation, optimization, and signoff for complex NSP designs.
• Architect, implement, and optimize advanced clock distribution structures, including:
  • Clock H-trees, Clock mesh architectures, Clock spine methodologies, Hierarchical clock distribution across block and top-level designs, Clock gating and low-power clock distribution techniques
• Perform detailed SPICE simulation and transistor-level analysis of critical clock structures to understand clock waveform quality, delay, slew, sensitivity, and robustness across operating conditions.
• Analyze and debug clock-related:
  • Timing and clock skew, Dynamic and leakage power, Signal integrity and noise, On-chip variation, Jitter and clock uncertainty, Duty-cycle distortion, Slew and waveform degradation, Physical implementation and routing issues
• Drive clock convergence and signoff across multiple modes, process corners, voltage conditions, temperatures, and operating frequencies.
• Analyze clock distribution tradeoffs across performance, power, area, skew, insertion delay, variation, and robustness, and recommend appropriate clock architectures and implementation strategies.
• Provide technical feedback and guidance to block-level and top-level Physical Design engineers on:
  • Required clocking fixes, Clock tree/mesh/spine optimization opportunities, Clock routing and physical implementation issues, Timing and variation concerns, Power reduction opportunities, Potential signoff risks
• Collaborate closely with PLL, STA/timing, power, CAD, RTL, architecture, and implementation teams to align:
  • Clock source assumptions, PLL and clock-source characteristics, Jitter budgets, Clock uncertainty, Clock latency and skew targets, Variation assumptions, MMMC constraints, Clock signoff methodology
• Perform detailed clock timing analysis using Synopsys PrimeTime and correlate implementation, STA, extraction, and SPICE results where required.
• Work with implementation teams to develop and tune customized clock implementation recipes and methodologies for aggressive performance and power targets.
• Support clock-related ECO development and implementation during timing closure and tapeout convergence.
• Evaluate clock networks for IR-drop, EM, crosstalk, signal integrity, and reliability risks, and work with implementation and power-integrity teams to resolve issues before tapeout.
• Drive clock-related tapeout readiness and ensure all clock structures meet required timing, power, physical verification, and reliability signoff criteria.
• Develop and enhance clock analysis, debug, characterization, and implementation automation using TCL, Python, Perl, and Linux shell scripting.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of industry experience in ASIC/SoC Physical Design, with significant hands-on experience in high-performance clock implementation and timing closure.
• Proven experience taking complex ASIC/SoC designs through physical design convergence and successful tapeout.
• Deep hands-on expertise with advanced clock distribution methodologies, including:
  • Clock H-trees
  • Clock mesh
  • Clock spines
  • Hierarchical clock distribution
  • Clock gating and low-power clock implementation
• Strong understanding of:
  • Clock skew and insertion delay
  • Jitter and clock uncertainty
  • Slew and duty-cycle distortion
  • PVT and on-chip variation
  • Clock power optimization
  • Clock signal integrity
  • Clock-related IR/EM concerns
  • Multi-mode/multi-corner timing analysis
• Hands-on experience with SPICE simulation and the ability to analyze clock circuits and distribution structures at the transistor and waveform level.
• Strong experience with industry-standard Physical Design and signoff tools, including:
  • Synopsys Fusion Compiler / ICC2 and/or Cadence Innovus
  • Synopsys PrimeTime
  • RC extraction and signal-integrity analysis tools
  • Physical verification and DRC/LVS signoff flows
• Strong understanding of advanced-node timing, parasitics, variation, power integrity, and reliability effects on clock distribution.
• Proficiency in TCL, Python, Perl, and Linux/Unix environments.

Preferred Skills

• Experience developing and deploying custom clock methodologies for high-frequency designs rather than relying exclusively on conventional CTS approaches.
• Experience with advanced technology nodes and clock-design challenges associated with increased process variation, interconnect resistance, power density, and reduced voltage margins.
• Strong understanding of PLL behavior, jitter, clock-source modeling, and clock uncertainty budgeting.
• Experience correlating SPICE, STA, extraction, and physical implementation results to identify root causes of clock performance or signoff issues. Familiarity with Infinisim or PrimeClock a plus.
• Knowledge of dynamic power, IR-drop, electromigration, signal integrity, crosstalk, and reliability analysis as they relate specifically to high-performance clock networks.
• Experience working across hierarchical SoC implementation, including interaction between clock source, top-level clock distribution, and block-level clock networks.
• Ability to influence implementation methodology and provide clear technical guidance to block owners, top-level PD engineers, timing teams, and CAD teams.
• Strong analytical and debugging skills with the ability to drive complex clocking problems from initial characterization through root cause and final signoff.

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Pay rangeand Other Compensation & Benefits :

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