{"id":1723417,"url":"https://alion.io/job/qualcomm-physical-design-engineer-staff-to-sr-staff","title":"Physical Design Engineer- Staff to Sr. Staff","company":{"id":94,"name":"Qualcomm","domain":"qualcomm.com","url":"https://alion.io/company/qualcomm","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"C","score":69,"open_postings":1046,"ghost_share":0.25,"stale_share":0.149,"repost_share":0.458,"time_to_fill_p50_days":74,"computed_at":"2026-11-02T06:13:15Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":174400,"max":261600,"currency":"USD","period":"year","gross":null,"usd_annual":261600},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Innovus","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Unix","optional":false},{"name":"Rest-Assured","optional":true}],"status":"live","first_seen_at":"2026-09-28T00:00:00Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-11-03T01:40:25Z","board_verified":true,"closed_at":null,"days_open":36,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":36},"description":"Company:\nQualcomm Technologies, Inc.Job Area:\nEngineering Group, Engineering Group > ASICS EngineeringGeneral Summary:\nQCT’s NSP Physical Design Team is actively seeking a highly experienced Clock Physical Design Engineer to develop, optimize, and sign off advanced clocking solutions for next-generation NSP designs. The ideal candidate will have 10+ years of ASIC/SoC physical design experience, with deep expertise in high-performance clock architecture and implementation, including clock H-trees, clock mesh, and clock spine methodologies.\nThis role requires strong understanding of the complete clock path, from clock source and distribution architecture through block-level implementation and signoff. The engineer will work across physical design, timing, power, PLL, and CAD teams to optimize clock performance, power, variation, noise, and robustness across advanced technology nodes.\nMinimum Qualifications:\n• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.OR\nMaster's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.\nOR\nPhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.\nKey Responsibilities\nOwn and drive clock physical design methodology, implementation, optimization, and signoff for complex NSP designs.\nArchitect, implement, and optimize advanced clock distribution structures, including:Clock H-trees, Clock mesh architectures, Clock spine methodologies, Hierarchical clock distribution across block and top-level designs, Clock gating and low-power clock distribution techniques\n\nPerform detailed SPICE simulation and transistor-level analysis of critical clock structures to understand clock waveform quality, delay, slew, sensitivity, and robustness across operating conditions.\nAnalyze and debug clock-related:Timing and clock skew, Dynamic and leakage power, Signal integrity and noise, On-chip variation, Jitter and clock uncertainty, Duty-cycle distortion, Slew and waveform degradation, Physical implementation and routing issues\n\nDrive clock convergence and signoff across multiple modes, process corners, voltage conditions, temperatures, and operating frequencies.\nAnalyze clock distribution tradeoffs across performance, power, area, skew, insertion delay, variation, and robustness, and recommend appropriate clock architectures and implementation strategies.\nProvide technical feedback and guidance to block-level and top-level Physical Design engineers on:Required clocking fixes, Clock tree/mesh/spine optimization opportunities, Clock routing and physical implementation issues, Timing and variation concerns, Power reduction opportunities, Potential signoff risks\n\nCollaborate closely with PLL, STA/timing, power, CAD, RTL, architecture, and implementation teams to align:Clock source assumptions, PLL and clock-source characteristics, Jitter budgets, Clock uncertainty, Clock latency and skew targets, Variation assumptions, MMMC constraints, Clock signoff methodology\n\nPerform detailed clock timing analysis using Synopsys PrimeTime and correlate implementation, STA, extraction, and SPICE results where required.\nWork with implementation teams to develop and tune customized clock implementation recipes and methodologies for aggressive performance and power targets.\nSupport clock-related ECO development and implementation during timing closure and tapeout convergence.\nEvaluate clock networks for IR-drop, EM, crosstalk, signal integrity, and reliability risks, and work with implementation and power-integrity teams to resolve issues before tapeout.\nDrive clock-related tapeout readiness and ensure all clock structures meet required timing, power, physical verification, and reliability signoff criteria.\nDevelop and enhance clock analysis, debug, characterization, and implementation automation using TCL, Python, Perl, and Linux shell scripting.\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.\n10+ years of industry experience in ASIC/SoC Physical Design, with significant hands-on experience in high-performance clock implementation and timing closure.\nProven experience taking complex ASIC/SoC designs through physical design convergence and successful tapeout.\nDeep hands-on expertise with advanced clock distribution methodologies, including:Clock H-trees\nClock mesh\nClock spines\nHierarchical clock distribution\nClock gating and low-power clock implementation\n\nStrong understanding of:Clock skew and insertion delay\nJitter and clock uncertainty\nSlew and duty-cycle distortion\nPVT and on-chip variation\nClock power optimization\nClock signal integrity\nClock-related IR/EM concerns\nMulti-mode/multi-corner timing analysis\n\nHands-on experience with SPICE simulation and the ability to analyze clock circuits and distribution structures at the transistor and waveform level.\nStrong experience with industry-standard Physical Design and signoff tools, including:Synopsys Fusion Compiler / ICC2 and/or Cadence Innovus\nSynopsys PrimeTime\nRC extraction and signal-integrity analysis tools\nPhysical verification and DRC/LVS signoff flows\n\nStrong understanding of advanced-node timing, parasitics, variation, power integrity, and reliability effects on clock distribution.\nProficiency in TCL, Python, Perl, and Linux/Unix environments.\nPreferred Skills\nExperience developing and deploying custom clock methodologies for high-frequency designs rather than relying exclusively on conventional CTS approaches.\nExperience with advanced technology nodes and clock-design challenges associated with increased process variation, interconnect resistance, power density, and reduced voltage margins.\nStrong understanding of PLL behavior, jitter, clock-source modeling, and clock uncertainty budgeting.\nExperience correlating SPICE, STA, extraction, and physical implementation results to identify root causes of clock performance or signoff issues. Familiarity with Infinisim or PrimeClock a plus.\nKnowledge of dynamic power, IR-drop, electromigration, signal integrity, crosstalk, and reliability analysis as they relate specifically to high-performance clock networks.\nExperience working across hierarchical SoC implementation, including interaction between clock source, top-level clock distribution, and block-level clock networks.\nAbility to influence implementation methodology and provide clear technical guidance to block owners, top-level PD engineers, timing teams, and CAD teams.\nStrong analytical and debugging skills with the ability to drive complex clocking problems from initial characterization through root cause and final signoff.\nQualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\nTo all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\nEEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\nPay rangeand Other Compensation & Benefits :\n$174,400.00 - $261,600.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.\nIf you would like more information about this role, please contact Qualcomm Careers.","description_format":"text","description_chars":9666,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Autonomous Driving","Energy Efficiency","Car Electronics"],"lifecycle":[{"event":"open","at":"2026-10-02T21:23:27Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 55 · green card filings: 6","filings_12m":55,"filings_prev_12m":87,"green_card_filings_12m":6,"median_offered_wage_usd":122008,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":80,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.894,"p_room":0.9,"age_days":35,"expected_fill_days":74,"reasons":["conf:3","velocity","win:mid","comp:brand"],"computed_at":"2026-11-02T06:13:15Z"},"pay":{"stated_usd_annual":261600,"is_top_pay":true},"html_url":"https://alion.io/job/qualcomm-physical-design-engineer-staff-to-sr-staff","json_url":"https://alion.io/job/qualcomm-physical-design-engineer-staff-to-sr-staff.json","meta":{"generated_at":"2026-11-03T05:24:00Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":7408,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-04T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":94},"rest":"https://alion.io/mcp/rest/get_company?id=94"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fqualcomm-physical-design-engineer-staff-to-sr-staff"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fqualcomm-physical-design-engineer-staff-to-sr-staff"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fqualcomm-physical-design-engineer-staff-to-sr-staff"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/qualcomm-physical-design-engineer-staff-to-sr-staff\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fqualcomm-physical-design-engineer-staff-to-sr-staff"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":1723417}},{"tool":"search_jobs","arguments":{"company":"qualcomm.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":1723417},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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