{"id":754834,"url":"https://alion.io/job/qualcomm-senior-lead-post-silicon-validation-engineer-smmu","title":"Senior Lead Post-Silicon validation Engineer - SMMU","company":{"id":94,"name":"Qualcomm","domain":"qualcomm.com","url":"https://alion.io/company/qualcomm","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":71,"open_postings":1087,"ghost_share":0.231,"stale_share":0.14,"repost_share":0.453,"time_to_fill_p50_days":74,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":29000,"max_usd":67000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"OpenOCD","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"Verification & Validation","optional":false},{"name":"Cadence Palladium","optional":true},{"name":"Cadence Protium","optional":true},{"name":"CI/CD","optional":true},{"name":"GitLab CI","optional":true},{"name":"Jenkins","optional":true},{"name":"Jira","optional":true},{"name":"KVM","optional":true},{"name":"Linux","optional":true},{"name":"Rest-Assured","optional":true},{"name":"Siemens Veloce","optional":true},{"name":"Synopsys HAPS","optional":true}],"status":"live","first_seen_at":"2026-09-02T00:00:00Z","employer_posted_date":"2026-09-08","last_verified_at":"2026-10-24T03:19:44Z","board_verified":true,"closed_at":null,"days_open":52,"trust":{"level":"ok","repost_count":2,"flags":["repost"],"days_open":51},"description":"Company:\nQualcomm India Private LimitedJob Area:\nEngineering Group, Engineering Group > ASICS EngineeringGeneral Summary:\nWe’re looking for a hands-on validation engineer to own IP- and subsystem-level verification & validation of System MMU (SMMU) blocks within complex SoCs.\nYou will work across ARM-based architectures, MMU/SMMU translation flows, and the surrounding SoC infrastructure-clocks, resets, NoC/fabrics, coherency, and debug (JTAG) -to ensure functional correctness, performance, and robustness from pre-silicon through post-silicon phases.\nMinimum Qualifications:\n• Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\nOR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\nWhat You’ll Do (Key Responsibilities)\nOwn SMMU validation at block/IP and subsystem levels: coverage-driven test planning, stimulus development, checking/score boarding, and closure.\n\nDevelop test build reusable verification components for SMMU, including page table generators, translation fault injectors, and traffic generators.\n\nValidate system interactions: SMMU with ARM cores, MMU/TLB, NoC/Interconnect, coherency (ACE/CHI or equivalent), and clock/reset domains (including CDC and low-power/clock-gating scenarios).\n\nExercise page table formats and features: stage-1/stage-2 translations, ASIDs/VMIDs, context banks/stream IDs, MSI/IOMMU operations, address translation faults, and SVA/ATS (if applicable).\n\nDebug complex issues using JTAG and on-chip debug/trace infrastructure (ETM/STM/SWO), bring-up scripts, and logic analyzers; drive root cause with design/architecture teams.\n\nPerformance & stress validation: create stress scenarios (burst/atomic/ordering/ QoS), measure bandwidth/latency, and validate backpressure & throttling behavior through NoC.\n\nContribute to emulation/FPGA and post-silicon: port tests, build bare-metal validation, develop board bring-up sequences and lab automation.\n\nOwn quality metrics: functional coverage, code coverage, assertions, defect density/escape rates; author clear test/coverage reports and sign-off criteria.\n\nCollaborate cross-functionally with architecture, RTL design, firmware/driver, physical design, and validation teams to refine specs and close issues quickly.\n\nContinuously improve methodology, tools, and checkers; mentor junior engineers in best practices.\n\nMinimum Qualifications (Must-Haves)\nB.E/B.Tech/M.Tech in ECE/EE/CS or equivalent with 3-5 years of relevant experience.\n\nStrong ARM architecture knowledge (A-profile preferred): memory model, privilege levels, exception model, caches, TLBs, MMU concepts, and virtual memory flows.\n\nDeep understanding of SMMU/IOMMU fundamentals: stream IDs, context banks, translation stages, page table formats, fault handling, and device DMA interactions.\n\nFamiliar with NoC/interconnect protocols and coherency (e.g., AXI/ACE/CHI), ordering rules, QoS, and interop with SMMU.\n\nSolid grasp of clocks/resets and their impact on SMMU and NoC behavior; experience validating low-power states and clock gating effects.\n\nJTAG basics to intermediate: scan chains, boundary scan, run-control, breakpoints, basic scripting with OpenOCD/DS-5/Arm Development Studio or similar.\n\nProficient in debugging complex HW/SW issues, using waveforms (e.g., Verdi/DVE), traces, and logs to isolate root cause.\n\nScripting in Python/Perl/TCL/Shell for test automation, log parsing, and lab workflows.\n\nCritical thinking & learning agility: ability to infer failure modes from first principles, design edge-case tests, and quickly onboard new IP/flows.\n\nPreferred Qualifications (Good-to-Have)\nPrior tapeouts with SMMU or IOMMU IP (Arm SMMU v2/v3 or equivalent vendor IP).\n\nPost-silicon validation experience: lab bring-up, firmware integration, board-level debug.\n\nExperience with emulation/FPGA prototyping (Veloce, Palladium, Protium, HAPS).\n\nFamiliarity with Linux IOMMU framework, device trees/ACPI, and driver-level validation (DMA mappings, iommu_ops).\n\nKnowledge of PCIe (including ATS/PRI/PASID), CXL, or virtualization stacks (KVM/Hypervisors) and their interaction with SMMU.\n\nExposure to safety/security: memory isolation, SMMU faults as security boundaries, RAS features, error injection and detection.\n\nPerformance modeling/analysis; profiling tools; building synthetic traffic to characterize SMMU/NoC behavior.\n\nCI/CD for verification (Jenkins/GitLab CI), coverage dashboards, and regression triage at scale.\n\nTools & Environment\nLanguages/Methodology: ARM assembly, C for bare-metal tests, Python/TCL/Perl for scripting.\n\nEmu/FPGA: Veloce/RUMI\n\nVersioning/CI: Perforce, Jira.\n\nOS/Drivers: bare-metal frameworks.\n\nKey Performance Indicators (KPIs)\nTest plan completeness and functional/code coverage closure against SMMU spec and use-cases.\n\nDefect discovery rate and escape rate (pre- vs. post-silicon).\n\nTime-to-root-cause for complex issues; quality of triage documentation.\n\nRegression stability and automation coverage.\n\nPerformance validation completeness vs. targets (latency, bandwidth, QoS).\n\nExample Work Items You’ll Own\nCreate tests for stage-1 and stage-2 translations, ASID/VMID rollover, TLB shootdowns, and context switch stress.\n\nValidate device DMA through SMMU under NoC congestion and clock gating scenarios; confirm ordering and coherency guarantees.\n\nRun JTAG-based bring-up sequences to verify SMMU registers, enable translations, and capture trace for fault analysis.\n\nAutomate validation: configure IOMMU groups, map/unmap devices, inject faults, and parse kernel logs for health signals.\n\nEducation\nB.E/B.Tech or M.E/M.Tech in EE/ECE/CS (or equivalent).\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\nTo all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\nIf you would like more information about this role, please contact Qualcomm Careers.","description_format":"text","description_chars":7714,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","Car Electronics"],"lifecycle":[{"event":"open","at":"2026-09-11T16:54:35Z"},{"event":"close","at":"2026-09-11T19:54:38Z"},{"event":"reopen","at":"2026-09-12T19:53:34Z"},{"event":"close","at":"2026-09-12T22:53:34Z"},{"event":"reopen","at":"2026-09-13T23:50:53Z"},{"event":"close","at":"2026-09-14T02:57:07Z"},{"event":"reopen","at":"2026-09-18T10:44:57Z"}],"visa":[],"liveness":{"score":55,"band":"ok","label":"Likely open","p_open":1,"p_active":0.613,"p_room":0.9,"age_days":51,"expected_fill_days":74,"reasons":["conf:1","repost:2","velocity","win:mid","comp:brand"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/qualcomm-senior-lead-post-silicon-validation-engineer-smmu","json_url":"https://alion.io/job/qualcomm-senior-lead-post-silicon-validation-engineer-smmu.json","meta":{"generated_at":"2026-10-24T03:42:11Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":5870,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":94},"rest":"https://alion.io/mcp/rest/get_company?id=94"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fqualcomm-senior-lead-post-silicon-validation-engineer-smmu"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fqualcomm-senior-lead-post-silicon-validation-engineer-smmu"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fqualcomm-senior-lead-post-silicon-validation-engineer-smmu"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/qualcomm-senior-lead-post-silicon-validation-engineer-smmu\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fqualcomm-senior-lead-post-silicon-validation-engineer-smmu"}]}