{"id":2855322,"url":"https://alion.io/job/qualcomm-senior-rtl-design-engineer-2","title":"Senior RTL Design Engineer","company":{"id":94,"name":"Qualcomm","domain":"qualcomm.com","url":"https://alion.io/company/qualcomm","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":71,"open_postings":1087,"ghost_share":0.231,"stale_share":0.14,"repost_share":0.453,"time_to_fill_p50_days":74,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ho Chi Minh City, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":20000,"max_usd":46000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1777},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Formal Verification","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Rest-Assured","optional":true}],"status":"closed","first_seen_at":"2026-10-13T00:00:00Z","employer_posted_date":"2026-10-19","last_verified_at":"2026-10-22T08:48:23Z","board_verified":false,"closed_at":"2026-10-22T08:48:23Z","days_open":9,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":9},"description":"Company:\nQualcomm Vietnam Company LimitedJob Area:\nEngineering Group, Engineering Group > Hardware EngineeringGeneral Summary:\nThe SoC Design organization is seeking engineers to contribute to the integration and implementation of complex SoC and subsystem designs. This role focuses on RTL integration, design-quality assessment, synthesis, constraints, and front-end readiness for downstream implementation and verification.\nThe successful candidate will work with IP designers, SoC architects, design verification, physical design, DFT, emulation, firmware, and methodology teams across the global engineering organization.\nResponsibilities\nIntegrate RTL from multiple IPs, subsystems, and reusable design components into SoC-level and subsystem-level designs.\nDevelop and maintain top-level RTL wrappers, hierarchy, interconnect, connectivity, clock and reset structures, interrupt paths, and configuration logic.\nWork with standard SoC interfaces and protocols, including AXI, AHB, APB, memory, debug, interrupt, clock, reset, and power-management interfaces.\nCoordinate IP releases, integration dependencies, file lists, manifests, parameters, build configurations, and design collateral.\nRun and debug RTL compile/elaboration, lint, CDC, RDC, structural checks, formal connectivity, and synthesis flows.\nPrepare RTL, constraints, libraries, and configuration inputs for synthesis and downstream physical implementation.\nAnalyze synthesis reports for timing, area, power, high-fanout, unmapped logic, inferred structures, unconnected signals, and design-rule issues.\nCollaborate with physical design teams to resolve critical paths, timing-convergence issues, congestion risks, and implementation constraints.\nSupport functional equivalence, gate-level simulation, emulation, FPGA, ECO, and design-release readiness activities.\nInvestigate failures across RTL, tools, constraints, configuration, and build environments; identify root cause and drive corrective action.\nParticipate in design reviews, code reviews, integration reviews, methodology improvements, and technical documentation activities.\nLevel-Specific Expectations\nA. Engineer:\nExecute defined RTL integration and synthesis tasks; resolve routine connectivity, compilation, lint, CDC, and synthesis issues with guidance; document results and escalate risks early.\nB. Senior Engineer:\nOwn integration of blocks or subsystems; independently debug complex front-end issues; improve scripts and flows; coordinate effectively with partner teams.\nC. Staff/Senior Staff Engineer:\nLead integration or synthesis activities for major subsystems or SoC components; define technical approaches; drive closure of cross-functional issues and mentor engineers.\nD. Principal Engineer:\nProvide technical leadership across programs or methodologies; influence architecture and integration strategy; drive scalable automation, quality, and synthesis convergence; mentor senior technical contributors.\nMinimum Qualifications\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n3+ years of relevant work experience in RTL design, SoC integration, synthesis, ASIC/FPGA development, or a related area.\nExperience with Verilog or SystemVerilog RTL development and hierarchical design integration.\nExperience with RTL simulation, compilation/elaboration, lint, CDC/RDC, synthesis, or equivalent front-end design flows.\nKnowledge of digital design fundamentals, timing concepts, clock/reset design, bus protocols, and hardware/software interfaces.\nAbility to analyze technical problems, communicate root cause clearly, and work effectively in a distributed, cross-functional team.\nPreferred Qualifications\nMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\nExperience integrating complex SoCs, subsystems, infrastructure IP, NoC/interconnect, memory, debug, security, or power-management logic.\nHands-on experience with synthesis, timing constraints, timing analysis, area/power optimization, formal equivalence, ECO, or gate-level simulation.\nExperience with low-power design concepts, power intent, isolation, retention, multi-voltage design, clock-domain crossings, or reset-domain crossings.\nExperience with Python, Perl, Tcl, Shell, or similar scripting for flow automation, quality checks, reporting, and build management.\nExperience with internal or commercial EDA tools for simulation, lint, CDC, synthesis, formal verification, and implementation handoff.\nKnowledge of SoC release QA, connectivity signoff, design documentation, and reusable IP/subsystem delivery processes.\nSelf-motivated, detail-oriented, and comfortable taking ownership of ambiguous technical problems across organizational boundaries.\nMinimum Qualifications:\n• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\nOR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\nTo all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\nIf you would like more information about this role, please contact Qualcomm Careers.","description_format":"text","description_chars":7017,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Autonomous Driving","RF & Wireless Hardware","Car Electronics"],"lifecycle":[{"event":"open","at":"2026-10-19T14:35:42Z"},{"event":"close","at":"2026-10-22T08:48:23Z"}],"visa":[],"liveness":null,"pay":null,"html_url":"https://alion.io/job/qualcomm-senior-rtl-design-engineer-2","json_url":"https://alion.io/job/qualcomm-senior-rtl-design-engineer-2.json","meta":{"generated_at":"2026-10-24T06:22:27Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":9229,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":94},"rest":"https://alion.io/mcp/rest/get_company?id=94"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fqualcomm-senior-rtl-design-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fqualcomm-senior-rtl-design-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fqualcomm-senior-rtl-design-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/qualcomm-senior-rtl-design-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fqualcomm-senior-rtl-design-engineer-2"}]}