{"id":47603,"url":"https://alion.io/job/qualcomm-server-cpu-clock-physical-design-engineer-staff-level-cambridge-uk","title":"Server CPU Clock Physical Design Engineer, Staff level - Cambridge, UK","company":{"id":94,"name":"Qualcomm","domain":"qualcomm.com","url":"https://alion.io/company/qualcomm","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"C","score":69,"open_postings":1050,"ghost_share":0.25,"stale_share":0.149,"repost_share":0.456,"time_to_fill_p50_days":74,"computed_at":"2026-11-01T06:10:25Z"}},"role":"DevOps","role_family":"DevOps","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Cambridge, United Kingdom"],"countries":["GB"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":99000,"max_usd":206000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":12},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Rest-Assured","optional":true}],"status":"live","first_seen_at":"2026-07-02T00:00:00Z","employer_posted_date":"2026-10-27","last_verified_at":"2026-11-01T15:14:19Z","board_verified":true,"closed_at":null,"days_open":122,"trust":{"level":"ok","repost_count":2,"flags":["repost"],"days_open":122},"description":"Company:\nQualcomm Technologies International LtdJob Area:\nEngineering Group, Engineering Group > CPU EngineeringGeneral Summary:\nJob Overview\nQualcomm is seeking an experienced CPU Clock Physical Design Engineer to join the Nuvia Data Center CPU team in Cambridge, UK. The team is developing next-generation, high-performance, power-efficient custom CPU technology for advanced compute and server-class platforms that will help transform the industry.\nIn this role, you will help define, implement, and optimize best-in-class clock generation and distribution solutions for high-frequency CPU designs. You will work closely with microarchitecture, RTL design, CAD, circuit design, block-level physical design, and top-level physical design teams to deliver robust, low-skew, low-power clocking solutions for next-generation CPUs.\nThis is a high-impact technical role for engineers who enjoy solving complex clocking, timing, power, and implementation challenges. You will have the opportunity to influence CPU clocking architecture and methodology from early design planning through physical implementation, signoff, and silicon correlation.\nThis position is open for Staff Engineer level, with scope, ownership, and technical leadership scaled according to experience.\nKey Responsibilities will include\nAs a Server CPU Clock Physical Design Engineer, you will:\nDefine and drive the overall clock generation and clock distribution methodology for next-generation data center CPU designs.\nWork with microarchitecture, RTL, CAD, circuit, block-level physical design, and top-level physical design teams to understand, implement, and validate CPU clocking requirements.\nArchitect, implement, and optimize low-skew, low-power clock networks using approaches such as clock H-trees, clock mesh, clock spines clocking methodologies\nPartner with CAD and physical design teams to develop and deploy clocking techniques that optimize skew, latency, clock power, timing margin, routability, and design convergence.\nUse SPICE simulation and circuit-level analysis to validate clock circuits, clock paths, and electrical behaviour across process, voltage, and temperature conditions.\nAnalyse and debug clock-related timing, power, noise, variation, and physical implementation issues across multiple modes, corners, and operating conditions.\nProvide feedback and guidance to block-level and top-level physical design engineers on required clocking fixes, optimization opportunities, and signoff risks.\nCollaborate with PLL, timing, power, CAD, and implementation teams to align clock source assumptions, jitter budgets, clock uncertainty, and signoff methodology.\nDevelop, document, and improve clock construction, analysis, and validation flows for future CPU generations.\nFor Staff-level candidates, provide technical leadership, mentor engineers, influence cross-functional methodology, and drive resolution of critical clocking challenges.\nRequired Skills and Experience\nWe are looking for candidates with strong experience in CPU clocking, physical design, timing, and circuit-aware implementation.\nThe ideal candidate will have:\nStrong experience in the construction and analysis of low-skew and low-power clock generation and distribution networks.\nHands-on experience with clock distribution structures and methodologies such as Clock H-tree, Clock Mesh, Clock Spines\nStrong understanding of CTS, clock balancing, insertion delay, skew optimization, useful skew, clock power reduction, and clock latency trade-offs.\nGood understanding of device physics, RC delay, signal integrity, variation, and electrical effects that influence clock quality and timing robustness.\nProficiency in SPICE simulation and analysis for circuit design, clock-path validation, and electrical verification.\nStrong understanding of static timing analysis and the interaction between clock architecture, timing closure, jitter, uncertainty, OCV/AOCV/POCV, setup/hold closure, and signoff quality.\nAbility to debug complex clocking issues across implementation, timing, power, noise, variation, and circuit domains.\nExperience working with industry-standard EDA implementation and signoff flows for physical design, timing analysis, power analysis, and physical verification.\nStrong communication skills and the ability to work effectively with global, cross-functional engineering teams.\nMinimum Qualifications\nCandidates should typically have one of the following:\nBachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.\nOR\nMaster’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.\nOR\nPhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in CPU design, physical implementation, clock design, or circuit-aware methodology.\nThe role is intended for experienced candidates and is open for Staff Engineer level.\nPreferred Qualifications\nExperience in any of the following areas would be highly valuable:\nExperience defining or deploying clock methodology across multiple designs, projects, or technology generations.\nStrong background in chip-level or top-level physical design, block integration, standard-cell optimization, and clock construction.\nExperience working in advanced semiconductor process nodes, especially 7nm and below.\nProficiency with PLL specifications, clock source modelling, skew estimation, jitter budgeting, and jitter measurements. Experience with high-frequency CPU or high-performance compute clocking.\nExperience with power-aware clocking, clock gating, resonant or mesh-based clocking strategies, and clock power optimization.\nFamiliarity with multi-corner multi-mode timing closure and variation-aware implementation methodologies.\nExperience developing automation or analysis flows using TCL, Python, Perl, or similar scripting languages.\nFor Staff-level candidates, demonstrated ability to lead technical initiatives, influence cross-functional teams, define methodology, and mentor other engineers.\nWhat We Value\nWe are especially interested in engineers who:\nHave deep clocking, timing, and physical design fundamentals.\nEnjoy solving difficult clock distribution, skew, jitter, power, and signoff challenges.\nCan balance circuit-level detail with top-level implementation and product-level constraints.\nAre passionate about enabling high-frequency, power-efficient data center CPU designs.\nBring a structured, analytical, and data-driven approach to debug and methodology improvement.\nCommunicate clearly across microarchitecture, RTL, circuits, CAD, timing, and physical design teams.\nDemonstrate ownership, technical curiosity, and a continuous-improvement mindset.\nBenefits and Perks\nAt Qualcomm, you will be part of a collaborative engineering culture focused on innovation, technical excellence, and meaningful product impact.\nWe offer:\nCompetitive compensation package, including base salary, performance-related bonus, and equity opportunities.\nEmployee Stock Purchase Plan and equity programs supporting employee share ownership and long-term participation in Qualcomm’s success.\nPension and retirement support, including a matching pension scheme.\nHealth and wellbeing benefits, including medical, life, income protection, and wellbeing resources.\nMaternity, paternity, family, and extended leave support to help employees balance professional and personal commitments.\nEducation assistance and tuition support to enable continued learning and professional development.\nRelocation and immigration support where applicable, particularly for strong candidates moving to join the Cambridge team.\nEmployee assistance and resilience programs supporting mental wellbeing, balance, and personal resilience.\nOpportunities to connect through employee networks, community programs, volunteering, and social groups that support inclusion, collaboration, and community engagement.\nSubsidised wellbeing and lifestyle benefits, which may include gym or fitness support, bicycle purchase schemes, and employee clubs.\nA flexible, collaborative, and technically challenging work environment, with the opportunity to work alongside highly skilled engineers on advanced CPU technology.\nWhy Join the Nuvia Data Center CPU Team in Cambridge?\nCambridge is Qualcomm’s largest office in the UK, with approximately 400 team members across engineering, business strategy, and support functions. From an engineering perspective, the Cambridge site includes teams focused on RF and PMU analog design, digital design and verification, digital physical design, embedded software, packaging, and post-silicon validation. Target products include high-performance CPUs and GPUs, ultra-low-power IoT devices, and wearables such as smart glasses, smart watches, and earbuds.\nThe Nuvia Data Center CPU team is building advanced custom CPU technology for next-generation compute platforms. As a CPU Clock Physical Design Engineer, you will play a key role in shaping the clocking architecture and physical implementation methodology that enables high-frequency, power-efficient server-class CPU products.\nThis is an opportunity to work on technically demanding CPU clocking challenges, influence future-generation design methodology, and make a direct impact on world-class silicon products\nMinimum Qualifications:\n• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.OR\nMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\nOR\nPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.\nQualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\nTo all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. 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