{"id":959878,"url":"https://alion.io/job/qualcomm-soc-design-implementation-engineer-up-to-principal-level","title":"SoC Design Implementation Engineer (Up to Principal Level)","company":{"id":94,"name":"Qualcomm","domain":"qualcomm.com","url":"https://alion.io/company/qualcomm","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":70,"open_postings":1083,"ghost_share":0.246,"stale_share":0.143,"repost_share":0.459,"time_to_fill_p50_days":74,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ho Chi Minh City, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":23000,"max_usd":53000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Rest-Assured","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-09-15T00:00:00Z","employer_posted_date":"2026-09-15","last_verified_at":"2026-10-29T02:42:13Z","board_verified":true,"closed_at":null,"days_open":44,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":44},"description":"Company:\nQualcomm Vietnam Company LimitedJob Area:\nEngineering Group, Engineering Group > Hardware EngineeringGeneral Summary:\nThe SoC Design organization is seeking engineers to contribute to the implementation and front-end readiness of complex SoC, subsystem, and IP designs. This role focuses on design constraints, synthesis, timing analysis, power-intent implementation, and implementation collateral required to deliver high-quality netlists to downstream Physical Design, Design Verification, DFT, emulation, and signoff teams.\nThe successful candidate will work closely with RTL Design, SoC Architecture, Design Verification, Physical Design, DFT, CAD/methodology, power-management, and program teams across the global engineering organization.\nThe role requires a strong understanding of the transformation from RTL to synthesized netlist, including constraint development, synthesis optimization, timing and QoR analysis, low-power implementation using UPF, and resolution of design issues across RTL, constraints, libraries, tools, and flow configuration.\nI. Responsibilities\nDesign Implementation and Front-End Readiness\nSupport implementation of complex SoC, subsystem, and IP designs from RTL through synthesis and handoff to downstream implementation teams.\n\nReview RTL hierarchy, design partitioning, clock and reset architecture, interface definitions, and implementation requirements.\n\nPrepare and maintain synthesis scripts, design configuration, file lists, libraries, operating conditions, scenarios, and implementation collateral.\n\nCoordinate design releases, dependencies, configuration updates, and implementation readiness across RTL, DV, DFT, PD, CAD, and architecture teams.\n\nAnalyze design quality and identify RTL, constraint, library, or flow issues affecting timing, power, area, reliability, or implementation convergence.\n\nSupport design reviews, implementation reviews, signoff reviews, and technical documentation activities.\n\nInvestigate failures across RTL, synthesis, constraints, UPF, libraries, tool setup, and build environments; identify root cause and drive corrective action.\n\nConstraint Development and Timing Readiness\nDevelop, review, and maintain timing constraints for block, subsystem, and SoC-level designs.\n\nCreate and validate clocks, generated clocks, clock relationships, clock uncertainty, input/output delays, loads, drive models, and operating scenarios.\n\nDefine and review timing exceptions, including false paths, multicycle paths, asynchronous paths, clock groups, and case analysis.\n\nSupport multi-mode, multi-corner timing analysis and ensure constraints are complete, consistent, and aligned with design intent.\n\nAnalyze timing reports, path groups, startpoints, endpoints, slack, path exceptions, clock latency, skew, and constraint coverage.\n\nDebug unconstrained paths, invalid constraints, conflicting exceptions, missing clocks, generated-clock issues, and constraint-propagation problems.\n\nCollaborate with RTL and Physical Design teams to resolve critical paths, high-fanout issues, excessive buffering, logic depth, congestion risks, and timing-convergence challenges.\n\nReview constraints for synthesis, formal equivalence, DFT, static timing analysis, and physical implementation consistency.\n\nDevelop constraint-quality checks and automation to improve constraint completeness, consistency, and reuse across projects.\n\nSynthesis and Netlist Generation\nRun and debug RTL synthesis for blocks, subsystems, and SoC-level designs using industry-standard synthesis flows.\n\nGenerate and review synthesis netlists, reports, databases, timing views, and implementation handoff collateral.\n\nAnalyze synthesis results for timing, area, power, high-fanout nets, unmapped logic, inferred structures, unconnected signals, and optimization quality.\n\nTune synthesis options, compile strategies, effort levels, retiming or optimization settings, and flow configuration to improve QoR while preserving design intent.\n\nIdentify and resolve issues involving black boxes, missing or mismatched libraries, unresolved references, unintended latches, X-propagation, multiple drivers, and synthesis warnings.\n\nSupport synthesis quality-of-results tracking and compare changes across RTL, constraints, libraries, tool versions, and implementation configurations.\n\nDeliver clean, traceable, and reproducible netlists for Physical Design, DFT, formal equivalence, emulation, gate-level simulation, and signoff activities.\n\nPartner with RTL designers to recommend RTL changes that improve timing, area, power, synthesis quality, and downstream implementation convergence.\n\nExperience with UPF and low-power implementation is a plus\nDevelop, integrate, review, and maintain UPF-based power intent for blocks, subsystems, and SoC designs.\n\nDefine and validate power domains, supply networks, supply sets, power states, isolation strategies, level-shifter strategies, retention requirements, and related low-power structures.\n\nEnsure UPF intent is consistent with RTL hierarchy, power architecture, voltage domains, clock/reset behavior, and implementation requirements.\n\nRun and debug power-intent checks, including missing or conflicting supplies, invalid domain crossings, incorrect isolation placement, level-shifter issues, retention mismatches, and incomplete power-state definitions.\n\nAnalyze synthesis results involving isolation cells, level shifters, retention cells, always-on logic, power switches, and other low-power implementation elements.\n\nCollaborate with architecture, RTL, PD, DFT, verification, and power-management teams to resolve power-intent interpretation and implementation issues.\n\nSupport low-power equivalence, power-aware simulation, implementation handoff, and signoff readiness.\n\nImprove UPF methodology, reusable templates, validation checks, and automation across projects.\n\nQuality, Debug, and Cross-Functional Collaboration\nDrive implementation quality closure across lint, CDC/RDC, connectivity, synthesis, constraints, UPF, formal, and release-readiness checks.\n\nDebug tool failures and design-quality issues using logs, reports, databases, waveforms, and automated analysis.\n\nWork with CAD and methodology teams to improve flow robustness, runtime, capacity, repeatability, and ease of adoption.\n\nDocument implementation assumptions, constraints, exceptions, known issues, methodology decisions, and handoff requirements.\n\nMentor engineers and share best practices in synthesis, timing constraints, UPF, debug, automation, and implementation methodology.\n\nII. Level Expectations\nEngineer\nExecute assigned implementation, constraint, synthesis, and UPF tasks with guidance from senior engineers.\n\nAnalyze basic timing, synthesis, and power-intent reports and assist with issue triage and closure.\n\nMaintain scripts, configuration, reports, and implementation collateral according to established methodology.\n\nCollaborate effectively with partner teams and escalate issues with clear technical information.\n\nSenior Engineer\nIndependently own implementation activities for blocks or subsystems from setup through synthesis and handoff.\n\nDevelop and validate timing constraints, synthesis flows, and UPF implementation for assigned design areas.\n\nDrive root-cause analysis and closure of timing, QoR, power-intent, and flow issues across multiple teams.\n\nContribute to methodology improvements, automation, technical reviews, and mentoring.\n\nStaff /Senior Staff Engineer\nLead implementation of major subsystems or complex SoC design areas, including constraints, synthesis, and low-power intent.\n\nDefine technical plans, implementation strategy, quality criteria, and handoff requirements.\n\nResolve complex cross-functional issues involving RTL, architecture, tools, libraries, timing, power, and physical implementation.\n\nDrive reusable methodology, automation, QoR improvement, and technical alignment across projects.\n\nPrincipal Engineer\nEstablish technical direction for SoC design implementation, synthesis, constraints, and UPF methodology across programs.\n\nLead architecture-level decisions that affect timing closure, power intent, implementation convergence, and design quality.\n\nInfluence cross-functional organizations and resolve the most complex technical risks and escalations.\n\nDefine scalable flows, standards, automation, and best practices for future SoC programs and mentor senior technical leaders.\n\nIII. Minimum Qualifications\nBachelor’s degree in Electrical Engineering, Computer Engineering, or a related field; a Master’s degree is preferred.\n\n3+ years of relevant experience in RTL design, SoC integration, synthesis, ASIC/FPGA development, or front-end implementation.\n\nExperience with at least one RTL development or front-end implementation flow from design through synthesis or implementation handoff.\n\nKnowledge of Verilog or SystemVerilog and familiarity with RTL design and SoC integration concepts.\n\nExperience developing or reviewing timing constraints and analyzing synthesis or static timing reports.\n\nUnderstanding of clocks, resets, interfaces, timing exceptions, design hierarchy, and implementation tradeoffs.\n\nGood communication, problem-solving, ownership, and cross-functional collaboration skills.\n\nPreferred Qualifications\nExperience with synthesis tools, static timing analysis tools, equivalence checking, lint, CDC/RDC, or related front-end quality tools.\n\nPractical experience with UPF, power domains, isolation, level shifters, retention, power states, or power-aware verification.\n\nExperience with multi-mode, multi-corner constraints and timing closure across block, subsystem, or SoC designs.\n\nKnowledge of ASIC implementation flows, DFT, physical design handoff, emulation, FPGA prototyping, or gate-level simulation.\n\nProficiency in Tcl, Python, Perl, Shell, or similar scripting languages for flow automation and report analysis.\n\nExperience with AXI, AHB, APB, or other standard on-chip interfaces.\n\nExperience working in a large, globally distributed semiconductor engineering organization.\n\nIV. Technical Skills\nRTL: Verilog, SystemVerilog, RTL hierarchy, clock/reset structures, interface integration, and synthesis coding practices.\n\nConstraints: clocks, generated clocks, I/O delays, exceptions, clock groups, uncertainty, scenarios, and constraint validation.\n\nSynthesis: RTL-to-gate compilation, QoR analysis, timing/area/power optimization, netlist generation, and synthesis debug.\n\nLow Power: UPF, power domains, supply sets, isolation, level shifters, retention, power states, and power-aware implementation.\n\nQuality and Signoff: lint, CDC/RDC, formal connectivity, equivalence, timing analysis, gate-level simulation, and implementation handoff.\n\nAutomation: Tcl, Python, Perl, Shell, report parsing, flow integration, regression infrastructure, and methodology development.\n\nMinimum Qualifications:\n• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\nOR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. 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