{"id":2899381,"url":"https://alion.io/job/qualcomm-soc-design-verification-engineer-7","title":"SoC Design Verification Engineer","company":{"id":94,"name":"Qualcomm","domain":"qualcomm.com","url":"https://alion.io/company/qualcomm","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":72,"open_postings":1175,"ghost_share":0.222,"stale_share":0.123,"repost_share":0.468,"time_to_fill_p50_days":74,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ho Chi Minh City, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":16000,"max_usd":37000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":775},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Formal Verification","optional":true},{"name":"Rest-Assured","optional":true}],"status":"closed","first_seen_at":"2026-10-16T00:00:00Z","employer_posted_date":"2026-10-19","last_verified_at":"2026-10-21T12:49:04Z","board_verified":false,"closed_at":"2026-10-21T12:49:04Z","days_open":5,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":5},"description":"Company:\nQualcomm Vietnam Company LimitedJob Area:\nEngineering Group, Engineering Group > Hardware EngineeringGeneral Summary:\nThe SoC Design Verification organization is seeking engineers to contribute to the verification of complex SoC, subsystem, and IP designs. This role focuses on verification planning, testbench and test development, simulation, coverage closure, debug, and pre-silicon release readiness. The successful candidate will work with architects, RTL designers, integration and synthesis, physical design, firmware, emulation, and post-silicon teams across the global engineering organization.\nResponsibilities\nTranslate product, architecture, and block specifications into verification plans, test scenarios, functional coverage, and signoff criteria.\nDevelop and maintain SystemVerilog/UVM testbenches, sequences, drivers, monitors, scoreboards, reference models, assertions, checkers, and reusable verification components.\nCreate directed, constrained-random, assertion-based, and coverage-driven tests for functional, corner-case, error, reset, power-state, security, performance, and low-power behavior.\nVerify RTL integration, interfaces, register programming, interrupts, clocks, resets, power-management behavior, interconnect, coherency, and subsystem connectivity.\nRun and debug simulation, regression, lint, CDC, RDC, formal, emulation, FPGA, and gate-level verification flows as applicable.\nAnalyze failures and perform root-cause debug across RTL, testbench, configuration, generated collateral, tools, and environments.\nDefine, track, and close functional, code, assertion, toggle, and coverage metrics; identify verification gaps and improve stimulus quality.\nCollaborate with RTL, architecture, integration, and synthesis teams to review specifications, identify design issues early, and drive defect resolution.\nSupport emulation readiness, firmware bring-up, SoC integration testing, pre-silicon release, and post-silicon debug preparation.\nDevelop scripts and automation using Python, Perl, Tcl, Shell, or similar languages to improve regression, debug, reporting, and verification productivity.\nDocument verification plans, test results, coverage status, known limitations, waivers, and release recommendations.\nLevel-Specific Expectations\nA. Engineer\nExecute defined DV tasks for IPs and subsystems under technical guidance.\nDevelop tests, checkers, coverage models, and regression content; debug routine failures.\nSupport block and subsystem verification, documentation, and coverage closure.\nB. Senior Engineer\nOwn verification of one or more blocks or features from planning through coverage closure.\nIndependently develop reusable UVM components and lead complex debug.\nCoordinate issue resolution with RTL, architecture, and DV teams and mentor engineers.\nC. Staff/Senior Staff Engineer\nLead verification of major subsystems or SoC features across multiple teams.\nDefine verification methodology, automation, coverage, regression, and signoff approaches.\nDrive technical risk identification, cross-functional debug, and delivery against program milestones.\nD. Principal Engineer\nProvide technical leadership and set verification strategy for major SoC programs or domains.\nResolve complex architectural, verification, performance, and quality issues.\nEstablish scalable methodologies, influence cross-site execution, and mentor senior technical contributors.\nMinimum Qualifications\nBachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n3+ years of relevant work experience in ASIC, SoC, IP, FPGA, or hardware design verification.\nHands-on experience with SystemVerilog and verification environments such as UVM.\nExperience with simulation, regression execution, waveform debug, and functional coverage analysis.\nUnderstanding of digital design fundamentals, RTL, finite-state machines, protocols, clock/reset behavior, and SoC architecture.\nExperience with scripting or automation using Python, Perl, Tcl, Shell, or similar languages.\nStrong analytical, debugging, communication, and teamwork skills.\nPreferred Qualifications\nMaster’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\nExperience verifying complex SoCs, subsystems, processors, interconnect, memory systems, peripherals, security, or low-power designs.\nKnowledge of AMBA protocols including AXI, AHB, and APB; interrupts, DMA, coherency, register interfaces, and NoC/interconnect behavior.\nExperience with formal verification, assertion-based verification, CDC/RDC analysis, emulation, FPGA prototyping, gate-level simulation, or power-intent verification.\nExperience with coverage closure, verification signoff, test planning, release QA, and quality documentation.\nExperience with internal or commercial EDA tools for simulation, lint, CDC/RDC, formal verification, emulation, and coverage analysis.\nFor Staff and Principal levels: demonstrated technical leadership, methodology ownership, mentoring, and successful SoC delivery.\nMinimum Qualifications:\n• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\nTo all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\nIf you would like more information about this role, please contact Qualcomm Careers.","description_format":"text","description_chars":6961,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Autonomous Driving","RF & Wireless Hardware","Car Electronics"],"lifecycle":[{"event":"open","at":"2026-10-20T05:48:38Z"},{"event":"close","at":"2026-10-21T12:49:04Z"}],"visa":[],"liveness":null,"pay":null,"html_url":"https://alion.io/job/qualcomm-soc-design-verification-engineer-7","json_url":"https://alion.io/job/qualcomm-soc-design-verification-engineer-7.json","meta":{"generated_at":"2026-10-21T17:14:29Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":24279,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-22T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":94},"rest":"https://alion.io/mcp/rest/get_company?id=94"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fqualcomm-soc-design-verification-engineer-7"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fqualcomm-soc-design-verification-engineer-7"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fqualcomm-soc-design-verification-engineer-7"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/qualcomm-soc-design-verification-engineer-7\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fqualcomm-soc-design-verification-engineer-7"}]}