{"id":2926910,"url":"https://alion.io/job/qualcomm-soc-rtl-design-developer","title":"SoC RTL Design Developer","company":{"id":4454000,"name":"Qualcomm","domain":"qualcomm.co.in","url":"https://alion.io/company/qualcomm-4","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India","Chennai, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":30000,"max_usd":62000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":9,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-20T13:35:43Z","employer_posted_date":null,"last_verified_at":"2026-10-20T13:35:43Z","board_verified":false,"closed_at":null,"days_open":2,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":2},"description":"Requirements: \nExperience in Logic design /micro-architecture / RTL coding is a must.\nMust have hands-on experience with SoC design and integration for SoCs.\nExperience in Verilog/System-Verilog is a must.\nShould know AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIe, and SDCC.\nUnderstanding of Memory controller designs and microprocessors is an added advantage.\nHands-on experience in constraint development and timing closure.\nWork closely with the SoC verification and validation teams for pre/post Silicon debug.\nHands-on experience in low-power SoC design is required.\nExperience in Synthesis / Understanding of timing concepts for ASIC is required.\nHands-on experience in multi-clock designs Asynchronous interface is a must.\nExperience creating pad ring and working with the chip-level floorplan team is an added advantage.\nExperience in using the tools in ASIC development such as Lint, CDC, Design Compiler, and PrimeTime is required.\n\nMinimum Qualifications: \nBachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n8+ years of experience in digital front-end ASIC/RTL design.\nSkills\nahb, amba, apb, asic, axi, rtl, soc, system verilog, systemverilog, verilog","description_format":"text","description_chars":1595,"description_truncated":false,"requirements":{"experience_years_min":9,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response"],"lifecycle":[{"event":"open","at":"2026-10-20T13:35:43Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":1,"expected_fill_days":31,"reasons":["seen:1","win:early"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/qualcomm-soc-rtl-design-developer","json_url":"https://alion.io/job/qualcomm-soc-rtl-design-developer.json","meta":{"generated_at":"2026-10-22T17:08:25Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":17956,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4454000},"rest":"https://alion.io/mcp/rest/get_company?id=4454000"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fqualcomm-soc-rtl-design-developer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fqualcomm-soc-rtl-design-developer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fqualcomm-soc-rtl-design-developer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/qualcomm-soc-rtl-design-developer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fqualcomm-soc-rtl-design-developer"}]}