Staff Emulation Build Quality, Performance & Debug Engineer

Company:

Job Area:

General Summary:

Minimum Requirements:

Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Preferred Requirements:

7+ years of experience working in emulation and silicon environments.

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

Qualcomm's Emulation Team is part of the central SoC digital hardware organization responsible for the overall development and support of SoC pre-silicon platforms. The Emulation team works closely with architects, designers, verification engineers, software engineers, and customers.

The Emulation Performance, Quality, and Debug team is responsible for improving the efficiency, scalability, quality, and reliability of Qualcomm's pre-silicon emulation platforms. The team drives emulation build performance optimization, root-cause analysis of complex hardware and software issues, and development of methodologies that improve build quality and debug productivity across multiple SoC programs.

The team is currently seeking candidates with experience in the following technical disciplines, languages, and methodologies:

• Emulation Platforms (FPGA Prototyping, Veloce, Palladium), Emulation tools (Synthesis, Place and Route, Constraints, Clocking, Timing Closure), Build Performance Analysis, Build Quality Improvement, System Debug (Waveform generation and Content Debug support)
• SoC Functionality (CPU/DSP Core, Multimedia, IO, Peripherals, DDR, Modem, Bus Protocols)

Preferred Qualifications

7+ years of experience working in emulation and silicon environments. Candidates are expected to have experience in:

• Design, development, and deployment of uniform global methodologies for emulation build generation and debug across FPGA based emulation platforms of various configurations
• Driving emulation build performance improvements through analysis, optimization, automation, and methodology development
• Cross-site collaboration, vendor engagements, and executive communication
• Working independently to drive complex technical initiatives from problem identification through deployment of scalable solutions
• Collaboration across architecture, design, verification, software, CAD, and system teams to drive root-cause analysis and long-term corrective actions
• Mentoring and guiding junior engineers while providing technical leadership across projects and teams
• Pre-silicon prototyping for new SoC designs, including pre-silicon enablement and bring-up
• Bring-up of new FPGA emulation/prototyping hardware and software
• Debugging low level software and hardware issues
• Leading complex debug efforts involving emulation infrastructure, hardware design, software, and FPGA implementation issues
• Debug tools including JTAG and kernel debuggers
• Validation and debug of digital circuits
• Root-cause analysis of build failures, timing issues, clocking issues, and functional failures across emulation platforms
• CPU and SoC architectures, with solid understanding of SoC building blocks (interconnects, power management, PMIC, NoC, peripherals)
• Basic understanding of power and performance
• Expertise in Verilog / SystemVerilog
• Experience with C programming
• Scripting: Proficient in Python, TCL
• FPGA Expertise: Xilinx/Intel FPGAs, Tools, and timing closure techniques
• Development of metrics, infrastructure, and methodologies to improve emulation build quality, runtime performance, and debug efficiency
• Ability to independently identify technical gaps, propose innovative solutions, and drive adoption across multiple engineering teams

Proven track record of influencing technical direction and delivering results in highly cross-functional environments

Minimum Qualifications:

OR

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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