{"id":4068632,"url":"https://alion.io/job/qualitas-semiconductor-digital-physical-implementation-gyeongryeok","title":"Digital Physical Implementation (경력)","company":{"id":2146273,"name":"Qualitas Semiconductor","domain":"q-semi.com","url":"https://alion.io/company/q-semi","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greeting","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Seongnam, South Korea"],"countries":["KR"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Genus","optional":false},{"name":"Synopsys Design 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SystemVerilog 문법에 대한 이해와 RTL 구조 분석 능력을 보유하신 분\nLogic Synthesis 및 Timing Constraint(SDC) 작성·검증에 대한 이해를 갖추신 분\nStatic Timing Analysis(STA)의 기본 개념(Setup/Hold, Recovery/Removal 등)에 대한 이해를 갖추신 분\nCDC/RDC 동기화 회로 구조 및 메타스테이블 방지 설계에 대한 이해를 갖추신 분\n⭐우대사항\nSynthesis Tool(Synopsys Design Compiler, Cadence Genus 등) 활용 경험을 보유하신 분\nLint / CDC Tool(SpyGlass, Questa CDC, VC SpyGlass 등) 활용 경험을 보유하신 분\nSTA Tool(PrimeTime, Tempus 등) 활용 경험을 보유하신 분\nDFT Tool(Tessent, DFT Compiler, TetraMAX 등) 활용 경험을 보유하신 분\nATPG 패턴 검증(Gate-level Simulation) 및 Silicon Bring-up/테스트 경험을 보유하신 분\n채용절차\n서류 전형 → 온라인 인성 검사 → 대면 면접 → 처우 협의 및 최종 합격\n※ 전형 일정 및 결과는 지원 시 작성하신 이메일로 개별 안내 드립니다.\n유의사항\n면접 전형은 오프라인으로 진행하며 면접비를 지급합니다.\n위 내용은 기본 프로세스로, 필요 시 Reference Check 등의 전형이 추가되거나 변경될 수 있습니다.\n입사지원 서류에 허위사실이 발견될 경우, 채용확정 이후라도 채용이 취소될 수 있습니다.\n국가보훈대상자 및 장애인은 관련법규에 의거하여 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