{"id":3414822,"url":"https://alion.io/job/quantinuum-advanced-semiconductormems-layout-routing-engineer-1106","title":"Advanced Semiconductor/MEMS Layout & Routing Engineer - 1106","company":{"id":696,"name":"Quantinuum","domain":"quantinuum.com","url":"https://alion.io/company/quantinuum","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":78,"open_postings":10,"ghost_share":0,"stale_share":0.9,"repost_share":0,"time_to_fill_p50_days":46,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Brooklyn Park, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":115000,"max":145000,"currency":"USD","period":"year","gross":null,"usd_annual":145000},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"KLayout","optional":false},{"name":"Tanner L-Edit","optional":false}],"status":"live","first_seen_at":"2026-10-27T17:53:58Z","employer_posted_date":"2026-10-27","last_verified_at":"2026-10-30T22:43:23Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"We are seeking an Advanced Semiconductor/MEMS Layout & Routing Engineer in our Brooklyn Park, MN, Albuquerque, NM or Broomfield, CO location.\nJoin an R&D team developing next-generation ion trap technologies. In this role, you will translate complex device concepts into manufacturable mask layouts, working from initial design through verification and tapeout. You will collaborate with design engineers, fabrication scientists, cross-functional partners, external foundries, and mask suppliers to ensure layouts meet technical requirements, established layout practices, and applicable process design kit requirements.\nAll applicants for placement in safety-sensitive positions will be required to submit to a pre-employment drug test.\nKey Responsibilities:\nDevelop and refine mask layouts for next-generation ion trap devices using Cadence Virtuoso, klayout, scripting and related layout tools.\nPartner closely with design engineers and fabrication scientists to resolve layout challenges and support device development through PDK and design rule refinement.\nWork directly with multiple external foundries to align layouts and tapeout deliverables with applicable PDKs, process requirements, and foundry best practices.\nWork with our layout team, vendors and foundries to refine workflows and help enable significant cycle time speedups through identifying areas for automation and AI/ML implementation\nYOU MUST HAVE:\nBachelor’s degree minimum\nMinimum 5 years' experience doing IC, MEMS or PCB layout using advanced EDA tools such as Cadence Virtuoso, Synopsis or L-Edit\nMinimum 2+ years’ experience with PDKs, layout hierarchy, routing, verification and tapeout processes\nDue to Contractual requirements, must be a U.S. Person. defined as, U.S. citizen permanent resident or green card holder, workers granted asylum or refugee status \nDue to national security requirements imposed by the U.S. Government, candidates for this position must not be a People's Republic of China national or Russian national unless the candidate is also a U.S. citizen. \nWE VALUE:\nAdvanced degree in electrical engineering, computer science, computer engineering, mechanical engineering, physics or a related area preferred\nExperience laying out masks for multiple external (i.e., non-captive) foundries in multiple technologies, supporting PDK integration and design rule changes\nFamiliarity with SKILL language script\nPhotonics component layout, place and routing\nFamiliarity with auto-routing tools in IC, PCB, MEMS layout and desire to leverage AI capabilities for layout\nExperience working in a cross-functional, R&D team environment.","description_format":"text","description_chars":2624,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":true,"languages":[{"language":"Russian","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Quantum Science & Computing","Quantum Computing Hardware"],"lifecycle":[{"event":"open","at":"2026-10-28T19:00:21Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely 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