{"id":802717,"url":"https://alion.io/job/quantinuum-analog-asic-electrical-engineer-966","title":"Analog ASIC Electrical Engineer - 966","company":{"id":696,"name":"Quantinuum","domain":"quantinuum.com","url":"https://alion.io/company/quantinuum","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":77,"open_postings":16,"ghost_share":0,"stale_share":0.938,"repost_share":0,"time_to_fill_p50_days":40,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Broomfield, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":136000,"max":170000,"currency":"USD","period":"year","gross":null,"usd_annual":170000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Apollo","optional":false}],"status":"live","first_seen_at":"2026-09-08T16:56:59Z","employer_posted_date":"2026-09-08","last_verified_at":"2026-10-12T19:41:56Z","board_verified":true,"closed_at":null,"days_open":34,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":34},"description":"We are seeking anAnalog ASIC Electrical Engineer in our Broomfield, CO, location. In this role, you will lead the development of ASIC designs for our Apollo and Lumos quantum computers (Quantinuum system roadmap). The ideal candidate will be an Electrical Engineer with a strong understanding of analog CMOS circuit design (high-voltage experience preferred), experience with transistor-level design and simulation, experience interacting with fabs, and an ability to integrate designs with complex electrical systems. This role will work alongside other ASIC designers as well as quantum architecture and packaging teams to refine the system architecture and develop scalable IP for further generations of Quantum Computers. Candidates should expect to be immersed in a fast-paced, multi-functional team-based environment with challenging technical obstacles to overcome where an individual with talent and initiative can stand out and thrive.\nQuantinuum believes that employees work better, more efficiently, and more collaboratively in close proximity to other employees, where ideas can be exchanged readily, and decisions can be made more quickly for the benefit of the Company and our customers. All employees should work at their assigned location; however, this role may offer the opportunity to work remotely up to 2 days per week, with approval.\nAll applicants for placement in safety-sensitive positions will be required to submit to a pre-employment drug test.\nKey Responsibilities:\nWork with an integrated product team including external partners to architect and implement ASICs in service of Quantinuum’s quantum computer roadmap and goals.\nDesign and optimize analog and mixed-signal integrated circuits in advanced CMOS process technologies.\nTranslate quantum computer requirements and customer needs into a comprehensive plan to integrate ASICs into the broader roadmap and address scalability challenges. Identify technical risks and develop mitigation strategies.\nTranslate system-level specifications into circuit architectures, design requirements, and verification plans.\nWork closely with system architects, digital designers, verification teams, and packaging teams to understand the impact of external subsystems on ASIC architecture and specification.\nDeploy ASICs in challenging environments such as cryogenic, ultra-high vacuum, and in proximity to noise-sensitive devices.\nDesign layouts for corresponding schematic blocks and ensure compliance with DRC, LVS, ERC, reliability, and design-for-manufacturing requirements.\nSupport analog and mixed-signal verification at block, subsystem, and full-chip levels. Co-author test plans and participate in silicon bring-up and debug activities.\nIdentify key enabling technology areas for ASIC development including feasibility studies, prototyping, and performing risk reduction activities to ensure smooth introduction into the roadmap.\nProvide technical expertise that informs future product development and process improvements across the organization.\nDeliver products and achieve program goals in an R&D and rapid prototyping environment.\nYOU MUST HAVE:\nBachelor’s Degree minimum\nMinimum 5+ years of IC design experience in a design engineering or R&D organization.\nMinimum 5+ years of experience with transistor-level design and simulation using industry-standard EDA tools.\nMinimum 3+ years of industry experience with the specification, development, verification, and test of analog ASIC technologies.\nDue to Contractual requirements, must be a U.S. Person defined as, U.S. citizen permanent resident or green card holder, workers granted asylum or refugee status.\nDue to national security requirements imposed by the U.S. Government, candidates for this position must not be a People's Republic of China national or Russian national unless the candidate is also a U.S. citizen.\nWE VALUE:\nMasters/PhD degree in Electrical Engineering or related field.\n10+ years of industry experience in an engineering or R&D environment.\nExperience in developing design workflows for ASICs from requirements through multiple design reviews, tapeout, and delivery into production.\nExperience with IC layout and high-density routing conditions.\nExperience with ASIC integration of digital and analog circuitry such as low-noise amplifiers, DACs/ADCs, passive/active signal filtering, analog/digital control loops, and low-noise switching.\nExperience in ASIC development for ultra-high vacuum and cryogenic environments with a deep understanding of how cryo temperatures affect circuit performance.\nExpertise in ASIC power, performance, and area trade-offs.\nExperience with the electrical engineering challenges inherent to Quantum Computers, especially those with ion-trap architectures, and how noise from electrical systems contributes to overall error rates.\nStrong communication skills and a proven ability to lead by example through execution of programmatic goals, consistently demonstrating decisive business impact, and continuously driving for improvement in a rapidly changing environment.","description_format":"text","description_chars":5063,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"Russian","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Quantum Science & Computing","Quantum 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