{"id":1969067,"url":"https://alion.io/job/ralliant-asic-design-manager","title":"ASIC Design Manager","company":{"id":2241821,"name":"Ralliant","domain":"ralliant.com","url":"https://alion.io/company/ralliant","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":{"grade":"A","score":93,"open_postings":18,"ghost_share":0,"stale_share":0.278,"repost_share":0,"time_to_fill_p50_days":55,"computed_at":"2026-10-10T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Boulder, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":103000,"max_usd":232000,"period":"year","method":"role_country_seniority_unknown","sample_n":2478},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-06T17:57:53Z","employer_posted_date":"2026-10-06","last_verified_at":"2026-10-11T23:21:21Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"ASIC Design Manager\nLocation: Louisville, CO or Beaverton, OR\nOrganization: ASIC Development Group, Tektronix\nOverview\nAt Tektronix, we believe innovation starts with our customers. For more than eighty years, we have delivered industry-leading test and measurement solutions that help engineers solve complex challenges around the world. Our engineering culture is collaborative, technically rigorous, and committed to innovation, continuous learning, and professional growth.\nWe are seeking an ASIC Design Manager to lead and grow our digital ASIC design and realization organization. ASICs are at the core of Tektronix’s next-generation instrumentation platforms, and this role is responsible for execution across the complete ASIC flow, from architecture and RTL development through IP integration, physical design, signoff, tapeout, and silicon bring-up.\nThis hands-on leadership role combines people management, vendor relations, technical direction, and project execution. You will lead engineers responsible for digital design, verification, and physical implementation while remaining engaged in critical architecture, implementation, timing closure, power integrity, and signoff decisions. The successful candidate will bring strong experience in ASIC development and the ability to guide a multidisciplinary team through complex technical and program challenges.\nKey Responsibilities\nLead, mentor, and develop a team of digital ASIC design, verification, and physical design engineers; establish clear priorities, support career growth, and foster a collaborative engineering culture.\nOwn the end-to-end digital ASIC development flow, including microarchitecture, RTL development, IP selection and integration, synthesis, constraints development, floorplanning, clock-tree synthesis, place-and-route, timing closure, and tapeout.\nSet technical direction for digital IP, subsystem design, full-chip integration, and physical implementation, balancing performance, power, area, reliability, reuse, cost, and schedule.\nDrive physical design planning and execution, including floorplanning, power-grid architecture, clock distribution, congestion analysis, routing optimization, engineering change orders, and design closure.\nHave knowledge of digital-on-top development flows for mixed-signal designs. \nOversee signoff activities, including static timing analysis, signal integrity, power integrity, IR-drop analysis, electromigration analysis, formal equivalence, DRC, LVS, and tapeout-readiness reviews.\nPartner with product and system architects to translate product requirements into ASIC specifications, partitioning strategies, interfaces, and performance targets.\nCoordinate execution across functional UVM verification, DFT, CAD, packaging, validation, product engineering, foundry, and external design-services teams.\nCollaborate with package design and process-technology teams on die planning, bump assignments, power delivery, thermal performance, manufacturability, and package integration.\nDevelop and execute project plans with program management, including schedules, resource plans, cost estimates, milestone tracking, and risk mitigation.\nDrive design quality through disciplined methodologies, technical reviews, lint and CDC readiness, implementation checks, and signoff criteria.\nImprove design flows, automation, and engineering practices to increase productivity, quality, reuse, and schedule predictability.\nSupport silicon bring-up, characterization, post-silicon debug, and production-readiness activities.\nRecruit and retain engineering talent, and manage contractors, external design-service providers, IP vendors, and other technical partners as needed.\nContribute directly to technical reviews and critical design or implementation work when it helps accelerate the team or reduce project risk.\nA Typical Day Might Include\nReviewing a microarchitecture proposal or RTL implementation and helping resolve an interface, performance, or integration issue.\nLeading a floorplan or implementation review and evaluating tradeoffs among timing, power, congestion, area, and reliability.\nWorking with physical design engineers to resolve timing, IR-drop, electromigration, signal-integrity, or physical-verification issues before tapeout.\nCollaborating with architects, packaging engineers, and foundry partners to refine system partitioning and die-to-package integration.\nMeeting with IP and design services vendors to discuss possible engagements.\nReviewing project status with program management, addressing technical risks, and adjusting priorities or resources.\nCoaching an engineer, conducting a technical review, or interviewing a candidate.\nMinimum Qualifications\nBachelor’s degree in Electrical Engineering, Computer Engineering, a related technical discipline, or equivalent practical experience.\nSignificant experience developing ASICs or complex digital integrated circuits, including digital design and physical implementation activities.\nExperience leading technical projects, mentoring engineers, or coordinating work across multidisciplinary engineering teams.\nStrong understanding of digital design methodologies, including microarchitecture, synthesizable SystemVerilog or Verilog RTL, IP integration, synthesis, constraints development, and static timing analysis.\nExperience with physical design and implementation, including several of the following: floor-planning, power planning, clock-tree synthesis, place-and-route, timing closure, engineering change orders, power integrity, or physical signoff.\nFamiliarity with ASIC verification, DFT, packaging, CAD, and silicon validation interfaces and handoffs.\nExperience using industry-standard ASIC design, implementation, timing, or signoff tools from Cadence, Synopsys, Siemens EDA, or equivalent providers.\nExperience supporting an ASIC through major development milestones such as design closure, tapeout, silicon bring-up, qualification, or production release.\nStrong communication, collaboration, organizational, and problem-solving skills, with the ability to work effectively across engineering, product, and program-management teams.\nPreferred Qualifications\nExperience managing or formally leading engineering teams, including hiring, coaching, career development, and resource planning.\nMaster’s or doctoral degree in Electrical Engineering, Computer Engineering, or a related field.\nExperience leading end-to-end digital ASIC or SoC implementation through tapeout.\nExperience with high-speed digital or mixed-signal ASICs, DSP architectures, data-converter interfaces, or instrumentation applications.\nExperience with multi-mode, multi-corner timing analysis; signal-integrity analysis; IR-drop and electromigration verification; or other physical signoff methodologies.\nExperience optimizing designs for performance, power, area, yield, reliability, and manufacturability.\nFamiliarity with flip-chip packaging, bump planning, package co-design, multi-chip modules, chiplets, or other advanced packaging technologies.\nExperience with FPGA prototyping, emulation, or other pre-silicon validation methods.\nExperience collaborating with foundries, OSAT partners, external IP vendors, EDA suppliers, or design-services providers.\nExperience improving ASIC development methodologies, automation, and team execution practices.\nWhy Join Tektronix?\nThis role offers the opportunity to shape the future of Tektronix instrumentation platforms while leading a talented engineering team responsible for strategic silicon development. You will influence technology direction, engineering methodology, and program execution while helping deliver ASIC solutions that enable the next generation of test and measurement innovation.","description_format":"text","description_chars":7726,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Continuous learning"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-06T18:29:04Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":3,"expected_fill_days":55,"reasons":["conf:1","velocity","win:early","comp:brand"],"computed_at":"2026-10-10T05:45:15Z"},"pay":null,"html_url":"https://alion.io/job/ralliant-asic-design-manager","json_url":"https://alion.io/job/ralliant-asic-design-manager.json","meta":{"generated_at":"2026-10-11T23:37:11Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":14728,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":2241821},"rest":"https://alion.io/mcp/rest/get_company?id=2241821"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fralliant-asic-design-manager"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fralliant-asic-design-manager"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fralliant-asic-design-manager"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ralliant-asic-design-manager\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fralliant-asic-design-manager"}]}