System Architect Verification Engineer
Confirmed on the employer's own hiring board on Oct 16, 2026. First seen by Alion on Sep 11, 2026. Ranovus scores A on the Alion truth index.
stem Architect Verification Engineer
Ottawa, ON, Canada | Full-Time | Ranovus
ABOUT RANOVUS
Ranovus is a fabless semiconductor company headquartered in Ottawa, Canada, developing next-generation co-packaged optics (CPO) solutions for AI and data center interconnects. Our Odin optical engine integrates a Quantum Dot Multi-Wavelength Laser, Photonic Integrated Circuit (PIC), and ASIC into a single co-packaged module - delivering the performance and density required by hyperscale AI infrastructure.
ABOUT THE ROLE
The System Architect Verification engineer develops and runs behavioral simulations and control verification tests for the optical engine (OE). Working in System Verilog and RTL, you will validate control algorithm, bring-up sequences, and link training algorithms before silicon is available - ensuring firmware and ASIC logic are correct before the first chip arrives.
KEY RESPONSIBILITIES
Develop and maintain System Verilog behavioral models of PIC, ASIC, and Laser subsystems for pre-silicon system simulation.
Build and run control verification testbenches: mission mode, bring-up sequences, link training, OE calibration, and fault recovery state machines.
Verify closed-loop (feedback) control algorithms used to calibrate and stabilize PIC components, such as bias and wavelength locking loops.
Perform RTL-level verification of ASIC control blocks in collaboration with the ASIC team.
Develop and maintain regression environments for control algorithm and bring-up validation.
Run corner case simulations across PVT (process, voltage, temperature) conditions and aging scenarios.
Correlate simulation results against lab measurements to validate model accuracy.
Support pre-silicon firmware validation in collaboration with the FW team.
Extend the system simulation environment as new blocks and features are added.
REQUIRED QUALIFICATIONS
S. in Electrical Engineering or related field with 6+ years of experience, or Ph.D. with 3+ years of experience, in digital or mixed-signal verification using SystemVerilog.
Familiarity with RTL simulation tools.
Understanding of closed-loop (feedback) control concepts for controlling PIC components (e.g., bias/wavelength locking control loops) and hardware bring-up sequencing.
Basic understanding of optical/photonic components such as micro-ring modulators (MRM), photodetectors, and similar devices.
Python or MATLAB for scripting, data analysis, and regression automation.
NICE TO HAVE
Experience with Verilog-A or Verilog-AMS for modeling analog or optical components.
Experience with optical or photonic system simulation.
Familiarity with SPICE or mixed-signal analog simulation.
Understanding of PAM4 link behavior and BER analysis.
Exposure to SerDes or high-speed interface IP verification.